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Increase test coverage, addresses #7 #9

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e6ef465
Try to make a test case for register offset
Sep 30, 2018
567476d
#7
Oct 3, 2018
e3c3d1a
Change immediate value to solve Cirrus CI failure
Oct 3, 2018
49f9278
comment all address modes
Oct 3, 2018
2580c92
uncomment address mode offset
Oct 3, 2018
a7ddbc1
uncomment address mode post-indexed
Oct 3, 2018
9cdcf9a
uncomment pre-indexed
Oct 3, 2018
8db1e69
comment pre-indexed
Oct 3, 2018
e44d2f7
Refactor one line to test covrage%
Oct 3, 2018
b15a7c8
Test memory register offset
Oct 3, 2018
67c8fc0
Test memory scaled register
Oct 3, 2018
35811e1
Add two testcases to memory insst - imm val
Oct 14, 2018
62144cd
Merge remote-tracking branch 'upstream/master'
Oct 14, 2018
fb16ac5
Change to hex
Oct 14, 2018
bc67544
Fix instruction code
Oct 14, 2018
dbdec22
comment out other tests
Oct 14, 2018
cd489d6
the effective PC is located two instructions ahead of the current one
Oct 14, 2018
2d2aff6
Use system.PC()
Oct 14, 2018
c284d20
Add missing )
Oct 14, 2018
d0569f0
comment out other codes
Oct 14, 2018
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46 changes: 46 additions & 0 deletions test/constexpr_tests.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -318,4 +318,50 @@ TEST_CASE("Test arbitrary code")
REQUIRE(TEST(thing.read_byte(1001) == 12)); // NOLINT This suppresses an initialization warning from catch2
}

/*
* Only load/store (LDR and STR) instructions can access memory
* Offset form:
* Immediate value
* Register
* Scaled register
*/
TEST_CASE("Test memory instructions - Immediate value")
{
CONSTEXPR auto system = run_instruction(cpp_box::arm::Instruction{ 0xe59f000c } // ldr r0, [pc, #12]
// cpp_box::arm::Instruction{ 0xe59f1016 }, // ldr r1, [pc, #12]
// cpp_box::arm::Instruction{ 0xe5902000 }, // ldr r2, [r0]
// cpp_box::arm::Instruction{ 0xe5812002 }, // str r2, [r1, #2] address mode: offset. Store
// cpp_box::arm::Instruction{ 0xe5a12004 }, // str r2, [r1, #4]! address mode: pre-indexed.
// TODO instruction not supported
// cpp_box::arm::Instruction{ 0xe4913004 }, // ldr r3, [r1], #4 address mode: post-indexed.
// TODO instruction not supported
// cpp_box::arm::Instruction{ 0xe5812000 } // str r2, [r1]
);

REQUIRE(TEST(system.registers[0] == (system.PC() + 12)));
// REQUIRE(TEST(system.registers[1] == 0x18));
// TODO REQUIRE(TEST(system.registers[2] == [[16]+2]));
}
/*
TEST_CASE("Test memory instructions - Register")
{
CONSTEXPR auto systest =
run_instruction(cpp_box::arm::Instruction{ 0xe7812002 } // str r2, [r1, r2] address mode: offset
// cpp_box::arm::Instruction{ 0x }, // str r2, [ r1, r2 ]! address mode: pre-indexed.
// TODO instruction not supported
// cpp_box::arm::Instruction{ 0xe }, // ldr r3, [r1], r2 address mode: post-indexed.
// TODO instruction not supported
);

// TODO REQUIRE(TEST());
}

TEST_CASE("Test memory instructions - Scaled register")
{
CONSTEXPR auto systest = run_instruction(cpp_box::arm::Instruction{ 0xe7913102 } // ldr r3, [r1, r2, LSL#2] address mode: offset
);

// TODO REQUIRE(TEST());
}
*/
#endif