Add sdpa sparse-attention backend (run without flash_attn/xformers)

[hanvansolo]

What

Adds sdpa as a third option for ATTN_BACKEND / SPARSE_ATTN_BACKEND, alongside the existing flash_attn and xformers. It implements the sparse full and windowed attention paths with torch.nn.functional.scaled_dot_product_attention, which ships with PyTorch and runs on every backend torch supports.

Why

Today the sparse attention modules hard-require flash_attn or xformers:

if ATTN == 'xformers':
    import xformers.ops as xops
elif ATTN == 'flash_attn':
    import flash_attn
else:
    raise ValueError(f"Unknown attention module: {ATTN}")

Both ship CUDA-only kernels, so they don't install on AMD/Intel GPUs (or on CPU), which blocks TRELLIS inference on that hardware. SDPA is a built-in, backend-agnostic fallback — it lets the image→mesh path run on ROCm / XPU / MPS / CPU with no extra dependency and no build step. On NVIDIA nothing changes: flash_attn/xformers stay the default and remain selectable; this is purely additive.

The image→mesh path uses only the full (DiTs) and windowed (mesh decoder, attn_mode="swin") modes, so those are what's implemented. serialized (which needs vox2seq) is left untouched — its module just imports cleanly under the new backend.

How

• trellis/modules/sparse/__init__.py: accept 'sdpa' for the attention backend env var and in set_attn.
• trellis/modules/sparse/attention/full_attn.py: SDPA branch. The packed variable-length sequences have no varlen SDPA kernel, so it runs one attention per sequence (a single call at batch size 1 — the inference case).
• trellis/modules/sparse/attention/windowed_attn.py: SDPA branch for both the uniform-window (batched SDPA) and ragged-window (per-window) cases.
• serialized_attn.py: import guard tolerates sdpa.

Correctness

Verified numerically equal to a naïve softmax-attention reference (max-abs error ~1e-6 for both the full varlen and windowed uniform cases).

Usage

export ATTN_BACKEND=sdpa

Tested

• AMD Radeon RX 6800 (RDNA2 / gfx1030), ROCm, Windows: full image→mesh runs end to end and produces a coherent mesh (combined with a non-CUDA sparse conv backend — a pure-torch torchsparse-compatible shim — which can follow as a separate change if there's interest).
• Output matches the flash_attn path within fp tolerance on NVIDIA.

Notes

The pure-torch path trades peak throughput for portability; on NVIDIA the native kernels remain the faster default. This PR only adds the option.

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