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8384223: RISC-V: entry_barrier_offset should consider UseZtso #557

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8384223: RISC-V: entry_barrier_offset should consider UseZtso #557

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16 changes: 9 additions & 7 deletions src/hotspot/cpu/riscv/gc/shared/barrierSetAssembler_riscv.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -228,7 +228,7 @@ void BarrierSetAssembler::nmethod_entry_barrier(MacroAssembler* masm, Label* slo
BarrierSetNMethod* bs_nm = BarrierSet::barrier_set()->barrier_set_nmethod();
Assembler::IncompressibleScope scope(masm); // Fixed length: see entry_barrier_offset()

Label local_guard;
Label local_guard, skip_barrier;
NMethodPatchingType patching_type = nmethod_patching_type();

if (slow_path == nullptr) {
Expand Down Expand Up @@ -290,24 +290,26 @@ void BarrierSetAssembler::nmethod_entry_barrier(MacroAssembler* masm, Label* slo
ShouldNotReachHere();
}

Label& barrier_target = slow_path == nullptr ? skip_barrier : *slow_path;
if (slow_path == nullptr) {
Label skip_barrier;
__ beq(t0, t1, skip_barrier);
__ beq(t0, t1, barrier_target, true /* is_far */);
} else {
__ bne(t0, t1, barrier_target, true /* is_far */);
}

if (slow_path == nullptr) {
__ rt_call(StubRoutines::method_entry_barrier());

__ j(skip_barrier);

__ bind(local_guard);

MacroAssembler::assert_alignment(__ pc());
__ emit_int32(0); // nmethod guard value. Skipped over in common case.
__ bind(skip_barrier);
} else {
__ beq(t0, t1, *continuation);
__ j(*slow_path);
__ bind(*continuation);
}

__ bind(skip_barrier);
}

void BarrierSetAssembler::c2i_entry_barrier(MacroAssembler* masm) {
Expand Down
26 changes: 13 additions & 13 deletions src/hotspot/cpu/riscv/gc/shared/barrierSetNMethod_riscv.cpp
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, 2025, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2018, 2026, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
Expand Down Expand Up @@ -41,17 +41,16 @@

static int slow_path_size(nmethod* nm) {
// The slow path code is out of line with C2.
// Leave a jal to the stub in the fast path.
return nm->is_compiled_by_c2() ? 1 : 8;
return nm->is_compiled_by_c2() ? 0 : 4;
}

static int entry_barrier_offset(nmethod* nm) {
BarrierSetAssembler* bs_asm = BarrierSet::barrier_set()->barrier_set_assembler();
switch (bs_asm->nmethod_patching_type()) {
case NMethodPatchingType::stw_instruction_and_data_patch:
return -4 * (4 + slow_path_size(nm));
return -4 * (5 + slow_path_size(nm));
case NMethodPatchingType::conc_instruction_and_data_patch:
return -4 * (15 + slow_path_size(nm));
return -4 * ((UseZtso ? 14 : 16) + slow_path_size(nm));
}
ShouldNotReachHere();
return 0;
Expand Down Expand Up @@ -103,6 +102,10 @@ class NativeNMethodBarrier {
}
_guard_addr = reinterpret_cast<int*>(instruction_address() + local_guard_offset(nm));
}

// Perform the checking as verification.
err_msg msg("%s", "");
assert(check_barrier(msg), "%s", msg.buffer());
}

int get_value() {
Expand All @@ -114,10 +117,6 @@ class NativeNMethodBarrier {
}

bool check_barrier(err_msg& msg) const;
void verify() const {
err_msg msg("%s", "");
assert(check_barrier(msg), "%s", msg.buffer());
}
};

// Store the instruction bitmask, bits and name for checking the barrier.
Expand All @@ -128,8 +127,8 @@ struct CheckInsn {
};

static const struct CheckInsn barrierInsn[] = {
{ 0x00000fff, 0x00000297, "auipc t0, 0 "},
{ 0x000fffff, 0x0002e283, "lwu t0, guard_offset(t0) "},
{ 0x00000fff, 0x00000297, "auipc t0, 0 " },
{ 0x000fffff, 0x0002e283, "lwu t0, guard_offset(t0)" },
/* ...... */
/* ...... */
/* guard: */
Expand All @@ -141,10 +140,11 @@ static const struct CheckInsn barrierInsn[] = {
// register numbers and immediate values in the encoding.
bool NativeNMethodBarrier::check_barrier(err_msg& msg) const {
address addr = instruction_address();
for(unsigned int i = 0; i < sizeof(barrierInsn)/sizeof(struct CheckInsn); i++ ) {
for (unsigned int i = 0; i < sizeof(barrierInsn) / sizeof(struct CheckInsn); i++) {
uint32_t inst = Assembler::ld_instr(addr);
if ((inst & barrierInsn[i].mask) != barrierInsn[i].bits) {
msg.print("Addr: " INTPTR_FORMAT " Code: 0x%x not an %s instruction", p2i(addr), inst, barrierInsn[i].name);
msg.print("Nmethod entry barrier did not start with auipc & lwu as expected. "
"Addr: " INTPTR_FORMAT " Code: 0x%x not an %s instruction.", p2i(addr), inst, barrierInsn[i].name);
return false;
}
addr += 4;
Expand Down