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    10 repositories

    • chip-design-book

      Public
      Introduction to Chip Design
      TeX
      •0•4•0•0•Updated Dec 8, 2025Dec 8, 2025

    • caravel_leros_2025

      Public
      Subsystem DTU test tapeout
      SystemVerilog
      •
      Apache License 2.0
      •1•3•0•0•Updated Dec 1, 2025Dec 1, 2025

    • chip-design-intro

      Public
      Introduction to Chip Design
      Scala
      •
      Other
      •5•48•0•0•Updated Oct 7, 2025Oct 7, 2025

    • soc-chip-2025

      Public
      DTU chips project on caravel
      Verilog
      •
      Apache License 2.0
      •0•1•0•0•Updated Jun 6, 2025Jun 6, 2025

    • dtu-soc-2025

      Public
      The SoC for the chip design course 2025
      Verilog
      •
      BSD 2-Clause "Simplified" License
      •1•9•0•0•Updated May 7, 2025May 7, 2025

    • patmos-chip-mpw7h

      Public
      Verilog
      •
      Apache License 2.0
      •0•0•0•0•Updated Nov 25, 2022Nov 25, 2022

    • os-chip-design

      Public
      TeX
      •
      BSD 2-Clause "Simplified" License
      •1•24•0•0•Updated Oct 24, 2022Oct 24, 2022

    • patmos-chip

      Public template
      https://caravel-user-project.readthedocs.io
      Verilog
      •
      Apache License 2.0
      •368•1•0•0•Updated Jun 16, 2022Jun 16, 2022

    • patmos

      Public
      Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
      VHDL
      •
      BSD 2-Clause "Simplified" License
      •74•3•0•0•Updated Jun 3, 2022Jun 3, 2022

    • ChipDay

      Public
      DTU Chip Day
      1•6•0•0•Updated Apr 26, 2022Apr 26, 2022