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WIP: Multi-tile configuration of CachePool #10

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WIP: Multi-tile configuration of CachePool #10

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18be6d2
[SRC] WIP: Add multi-tile support in xbar.
DiyouS Nov 21, 2025
93a103a
[SRC] WIP: Update pkg for multi-tile configuration.
DiyouS Nov 26, 2025
b7ab5e3
[SRC] WIP: Add group-level.
DiyouS Nov 26, 2025
b70f183
[SRC] WIP: add group-level.
DiyouS Nov 26, 2025
8132a9c
WIP: [SRC] multi-tile support.
DiyouS Dec 11, 2025
7b35ab6
[SRC] WIP: Move prepheral to the cluster level.
DiyouS Jan 5, 2026
cfc71fb
[TB] Fix a bug in testbench of incorrectly using negedge instead of p…
DiyouS Jan 5, 2026
36b6554
[SRC] WIP: Adapt package for readability, keep working on multi-tile …
DiyouS Jan 6, 2026
2efeaa5
[SRC] WIP: Adapt package for readability
DiyouS Jan 7, 2026
5290115
[SRC] WIP: continue work on multi-tile support.
DiyouS Jan 7, 2026
683f7f5
[SRC] Fix the core_id and tile_id.
DiyouS Jan 8, 2026
a7a78f7
[SRC] Change hardware barrier to the new two-level hardware barrier f…
DiyouS Jan 9, 2026
dfe9b0a
[SW] Add software for insitu cache byte/half-word/word access test.
Aquaticfuller Jan 7, 2026
835cc34
[SW] Add more info output for cache byte access test.
Aquaticfuller Jan 8, 2026
bf08961
[RTL] wire byte strobes into L1 data banks
Aquaticfuller Jan 9, 2026
36cf9b2
Update the insitu-cache dep which supports byte access.
Aquaticfuller Jan 9, 2026
13485e5
[SW] Add vector byte/half-word test.
Aquaticfuller Jan 9, 2026
6b49e50
[SCRIPT] Update the auto-benchmark scripts: 1.add new benchmarks; 2. …
Aquaticfuller Jan 13, 2026
b322716
[Lint] Fix a line length exceeds max linting issue.
Aquaticfuller Jan 13, 2026
1b5999a
[SRC] WIP: connect the cross-tile interconnection.
DiyouS Jan 13, 2026
4f16064
[SRC] Fix several warnings in simulation.
DiyouS Jan 13, 2026
fe27ce3
[SRC] Fix a comb loop in multi-tile configuration.
DiyouS Jan 15, 2026
8c3b6d9
[SRC] Support two-tile conifguration.
DiyouS Jan 15, 2026
541c6e3
[SRC] Clean code for multi-tile support.
DiyouS Jan 16, 2026
ca7d98f
[Runtime] Add tile id and number of tile functions in runtime.
DiyouS Jan 16, 2026
64f49ac
[CFG] Switch configurations to use 4 tile 16 cores by default.
DiyouS Jan 16, 2026
001f375
[SRC] Fix ID width mismatch and port width mismatch
DiyouS Jan 19, 2026
a9c96a2
[SW] WIP: Update dotp algorithm for better performance in multi-tile …
DiyouS Jan 19, 2026
0fcfcf5
[SW] Update the multi-tile dotp kernel.
DiyouS Jan 21, 2026
11e1cc1
[SW] Add optimized gemv kernel for multi-tile.
DiyouS Jan 21, 2026
7fa53a8
[CI] Update CI for multi-tile support.
DiyouS Jan 27, 2026
01a6604
[CI] Increase timeout to 5h.
DiyouS Jan 27, 2026
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3 changes: 1 addition & 2 deletions .gitlab-ci.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,7 @@ stages:
build-vsim:
extends: .base
stage: build
timeout: 5h
script:
- echo "Using CC=$CC"
- echo "Using CXX=$CXX"
Expand All @@ -44,6 +45,4 @@ build-vsim:

artifacts:
paths:
- software/build
- sim/bin
- util/auto-benchmark/logs
4 changes: 2 additions & 2 deletions Bender.lock
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Expand Up @@ -71,7 +71,7 @@ packages:
- common_verification
- register_interface
insitu-cache:
revision: 04f72a7ac7e9091f1820f0dac59bb778b134d7f7
revision: 57c0884166dd0f1b7c484633b437fe11d5d62c89
version: null
source:
Git: https://github.com/pulp-platform/Insitu-Cache.git
Expand All @@ -97,7 +97,7 @@ packages:
- common_cells
- tech_cells_generic
spatz:
revision: b60f7aee5e3be31facf566955aadbd5b6eac5da3
revision: 707ac676015eebceb30e1e09ef75bff1a06220a8
version: null
source:
Git: https://github.com/pulp-platform/spatz.git
Expand Down
4 changes: 4 additions & 0 deletions Bender.yml
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Expand Up @@ -29,12 +29,16 @@ sources:
- hardware/src/tcdm_cache_interco.sv
- hardware/src/tcdm_id_remapper.sv
- hardware/src/spatz_cache_amo.sv
- hardware/src/cachepool_tile_barrier.sv
- hardware/src/cachepool_cluster_barrier.sv
# Level 1
- hardware/src/cachepool_pkg.sv
- hardware/src/cachepool_cc.sv
# Level 2
- hardware/src/cachepool_tile.sv
# Level 3
- hardware/src/cachepool_group.sv

- hardware/src/cachepool_cluster.sv
# Level 4
- hardware/tb/cachepool_cluster_wrapper.sv
Expand Down
2 changes: 2 additions & 0 deletions Makefile
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Expand Up @@ -182,6 +182,7 @@ VLOG_DEFS = -DCACHEPOOL

# Cluster configuration
VLOG_DEFS += -DNUM_TILES=$(num_tiles)
VLOG_DEFS += -DNumRemotePortTile=$(num_remote_ports_per_tile)
VLOG_DEFS += -DNUM_CORES=$(num_cores)
VLOG_DEFS += -DDATA_WIDTH=$(data_width)
VLOG_DEFS += -DADDR_WIDTH=$(addr_width)
Expand Down Expand Up @@ -274,6 +275,7 @@ vsim: dpi ${SIMBIN_DIR}/cachepool_cluster.vsim

.PHONY: clean
clean: clean.sw clean.vsim
rm -rf $(HJSON_OUT)

########
# Lint #
Expand Down
12 changes: 7 additions & 5 deletions config/cachepool.hjson
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Expand Up @@ -12,7 +12,7 @@
data_width: 32,
id_width_in: 6, // fixed for now
id_width_out: 2, // fixed for now
user_width: 17,
user_width: 21,
axi_cdc_enable: false,
sw_rst_enable: true,
axi_isolate_enable: false,
Expand All @@ -29,9 +29,9 @@

// Spatz parameters
vlen: 512,
n_fpu: 0,
n_fpu: 4,
n_ipu: 4,
spatz_fpu: false,
spatz_fpu: true,
norvd: true,

// Timing parameters (fixed defaults; tweak in template if needed)
Expand All @@ -53,9 +53,11 @@
register_offload_rsp: true
},

// Repeat the compute core template N times (driven by 4)
nr_tiles: 4,

// Repeat the compute core template N times (driven by 16)
cores: [
{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" }
{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" }
],

icache: {
Expand Down
2 changes: 2 additions & 0 deletions config/cachepool.hjson.tmpl
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Expand Up @@ -53,6 +53,8 @@
register_offload_rsp: true
},

nr_tiles: ${num_tiles},

// Repeat the compute core template N times (driven by ${num_cores})
cores: [
${cores_array}
Expand Down
4 changes: 2 additions & 2 deletions config/cachepool_128.mk
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Expand Up @@ -9,10 +9,10 @@
#########################

# Number of tiles
num_tiles ?= 1
num_tiles ?= 4

# Number of cores
num_cores ?= 4
num_cores ?= 16

# Core datawidth
data_width ?= 32
Expand Down
8 changes: 4 additions & 4 deletions config/cachepool_512.mk
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Expand Up @@ -9,10 +9,10 @@
#########################

# Number of tiles
num_tiles ?= 1
num_tiles ?= 4

# Number of cores
num_cores ?= 4
num_cores ?= 16

# Core datawidth
data_width ?= 32
Expand Down Expand Up @@ -48,11 +48,11 @@ l1d_coal_window ?= 2
# L1 data cache number of ways per
l1d_num_way ?= 4

# L1 data cache size per tile (KiB)
# L1 data cache size **per tile** (KiB)
l1d_tile_size ?= 256

# L1 data cache tag width (TODO: should be calcualted)
l1d_tag_data_width ?= 52
l1d_tag_data_width ?= 92

####################
## CachePool CC ##
Expand Down
6 changes: 3 additions & 3 deletions config/cachepool_fpu_128.mk
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Expand Up @@ -9,10 +9,10 @@
#########################

# Number of tiles
num_tiles ?= 1
num_tiles ?= 4

# Number of cores
num_cores ?= 4
num_cores ?= 16

# Core datawidth
data_width ?= 32
Expand Down Expand Up @@ -43,7 +43,7 @@ l1d_size ?= 256
l1d_bank_factor ?= 1

# L1 coalecsing window
l1d_coal_window ?= 2
l1d_coal_window ?= 1

# L1 data cache number of ways per
l1d_num_way ?= 4
Expand Down
4 changes: 2 additions & 2 deletions config/cachepool_fpu_256.mk
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Expand Up @@ -9,10 +9,10 @@
#########################

# Number of tiles
num_tiles ?= 1
num_tiles ?= 4

# Number of cores
num_cores ?= 4
num_cores ?= 16

# Core datawidth
data_width ?= 32
Expand Down
8 changes: 5 additions & 3 deletions config/cachepool_fpu_512.mk
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Expand Up @@ -9,17 +9,19 @@
#########################

# Number of tiles
num_tiles ?= 1
num_tiles ?= 4

# Number of cores
num_cores ?= 4
num_cores ?= 16

# Core datawidth
data_width ?= 32

# Core addrwidth
addr_width ?= 32

num_remote_ports_per_tile ?= 1


######################
## CachePool Tile ##
Expand Down Expand Up @@ -52,7 +54,7 @@ l1d_num_way ?= 4
l1d_tile_size ?= 256

# L1 data cache tag width (TODO: should be calcualted)
l1d_tag_data_width ?= 52
l1d_tag_data_width ?= 92

####################
## CachePool CC ##
Expand Down
9 changes: 3 additions & 6 deletions config/config.mk
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Expand Up @@ -29,6 +29,8 @@ include $(CACHEPOOL_DIR)/config/$(config).mk
# Number of tiles
num_tiles ?= 1

num_remote_ports_per_tile ?= 1

# Number of cores
num_cores ?= 4

Expand Down Expand Up @@ -102,16 +104,11 @@ snitch_max_trans ?= 16
#########################
## AXI configuration ##
#########################
# --- AXI user width derived from L1D cacheline width ---
# supported widths only
ifneq ($(filter $(l1d_cacheline_width),128 256 512),$(l1d_cacheline_width))
$(error l1d_cacheline_width must be one of {128,256,512} (got $(l1d_cacheline_width)))
endif

ifeq ($(l1d_cacheline_width),512)
axi_user_width := 17
else ifeq ($(l1d_cacheline_width),256)
axi_user_width := 19
axi_user_width := 18
else ifeq ($(l1d_cacheline_width),128)
axi_user_width := 21
endif
Expand Down
4 changes: 2 additions & 2 deletions hardware/src/cachepool_cc.sv
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Expand Up @@ -55,8 +55,8 @@ module cachepool_cc
parameter type acc_issue_req_t = logic,
parameter type acc_issue_rsp_t = logic,
parameter type acc_rsp_t = logic,
parameter type dma_events_t = logic,
parameter type dma_perf_t = logic,
// parameter type dma_events_t = logic,
// parameter type dma_perf_t = logic,
/// FPU configuration.
parameter fpu_implementation_t FPUImplementation = fpu_implementation_t'(0),
/// Boot address of core.
Expand Down
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