Migrate hardware dependencies from Git submodules to Bender

.github/workflows/ci.yml

@@ -247,8 +247,8 @@ jobs:
       run: pip install -r python-requirements.txt
     - name: Build Control Registers
       run: |
-        git submodule update --init --recursive -- hardware/deps/register_interface
-        git apply hardware/deps/patches/register_interface.patch
+        make bender
+        make update-deps
         make -C hardware/src/control_registers clean
         make -C hardware/src/control_registers all
         git diff --ignore-submodules=dirty --exit-code
@@ -259,7 +259,7 @@ jobs:
     - uses: actions/checkout@v4
     - name: Regenerate opcodes
       run: |
-        make update_opcodes
+        make update-opcodes
         git diff --exit-code
 
   ####################
@@ -518,7 +518,7 @@ jobs:
       run: |
         # Don't regenerate previously build artifacts
         sudo apt install device-tree-compiler
-        make update_opcodes
+        make update-opcodes
         touch $GITHUB_WORKSPACE/software/runtime/encoding.h
         touch $GITHUB_WORKSPACE/hardware/src/bootrom.sv
         touch $GITHUB_WORKSPACE/hardware/deps/snitch/src/riscv_instr.sv

.github/workflows/lint.yml

@@ -67,8 +67,10 @@ jobs:
         fi
     - name: Check for trailing whitespaces and tabs
       run: |
-        git diff --check $base HEAD --          \
-            ':(exclude)**.def'                  \
-            ':(exclude)**.patch'                \
-            ':(exclude)toolchain/**'            \
-            ':(exclude)software/riscv-tests/**'
+        git diff --check $base HEAD --                       \
+            ':(exclude)**.def'                               \
+            ':(exclude)**.patch'                             \
+            ':(exclude)toolchain/**'                         \
+            ':(exclude)software/riscv-tests/**'              \
+            ':(exclude)software/runtime/control_registers.h' \
+            ':(exclude)hardware/src/control_registers/*.sv'

.gitlab/.gitlab-ci.yml

@@ -138,7 +138,7 @@ check-control-registers:
 check-opcodes:
   stage: test
   script:
-    - make update_opcodes
+    - make update-opcodes
     - git diff --exit-code
 
 # Software tests
@@ -218,7 +218,7 @@ unit-tests:
     - $CI_PROJECT_DIR/scripts/memora_retry.sh get tc-riscv-gcc
     - $CI_PROJECT_DIR/scripts/memora_retry.sh get riscv-isa-sim
     - $CI_PROJECT_DIR/scripts/memora_retry.sh get verilator-model
-    - make update_opcodes
+    - make update-opcodes
     - touch $ROOT_DIR/software/runtime/encoding.h
     - touch $ROOT_DIR/hardware/src/bootrom.sv
     - touch $ROOT_DIR/hardware/deps/snitch/src/riscv_instr.sv

.gitmodules

@@ -10,39 +10,9 @@
 [submodule "toolchain/verilator"]
 	path = toolchain/verilator
 	url = https://github.com/verilator/verilator.git
-[submodule "hardware/deps/axi"]
-	path = hardware/deps/axi
-	url = https://github.com/pulp-platform/axi.git
-[submodule "hardware/deps/cluster_interconnect"]
-	path = hardware/deps/cluster_interconnect
-	url = https://github.com/pulp-platform/cluster_interconnect.git
-[submodule "hardware/deps/common_cells"]
-	path = hardware/deps/common_cells
-	url = https://github.com/pulp-platform/common_cells.git
-[submodule "hardware/deps/common_verification"]
-	path = hardware/deps/common_verification
-	url = https://github.com/pulp-platform/common_verification.git
-[submodule "hardware/deps/register_interface"]
-	path = hardware/deps/register_interface
-	url = https://github.com/pulp-platform/register_interface.git
-[submodule "hardware/deps/tech_cells_generic"]
-	path = hardware/deps/tech_cells_generic
-	url = https://github.com/pulp-platform/tech_cells_generic.git
 [submodule "toolchain/riscv-opcodes"]
 	path = toolchain/riscv-opcodes
 	url = https://github.com/pulp-platform/riscv-opcodes.git
-[submodule "hardware/deps/apb"]
-	path = hardware/deps/apb
-	url = https://github.com/pulp-platform/apb.git
-[submodule "hardware/deps/fpnew"]
-	path = hardware/deps/fpnew
-	url = https://github.com/pulp-platform/cvfpu.git
-[submodule "hardware/deps/fpu_div_sqrt_mvp"]
-	path = hardware/deps/fpu_div_sqrt_mvp
-	url = https://github.com/pulp-platform/fpu_div_sqrt_mvp.git
 [submodule "hardware/deps/dram_rtl_sim"]
 	path = hardware/deps/dram_rtl_sim
 	url = https://github.com/pulp-platform/dram_rtl_sim.git
-[submodule "hardware/deps/cluster_icache"]
-	path = hardware/deps/cluster_icache
-	url = https://github.com/pulp-platform/cluster_icache.git

Bender.lock

@@ -1,16 +1,16 @@
 packages:
   apb:
-    revision: null
-    version: null
+    revision: 77ddf073f194d44b9119949d2421be59789e69ae
+    version: 0.2.4
     source:
-      Path: hardware/deps/apb
+      Git: https://github.com/pulp-platform/apb.git
     dependencies:
     - common_cells
   axi:
-    revision: null
-    version: null
+    revision: ac5deb3ff086aa34b168f392c051e92603d6c0e2
+    version: 0.39.2
     source:
-      Path: hardware/deps/axi
+      Git: https://github.com/pulp-platform/axi.git
     dependencies:
     - common_cells
     - common_verification
@@ -26,39 +26,39 @@ packages:
     - scm
     - tech_cells_generic
   cluster_interconnect:
-    revision: null
-    version: null
+    revision: 7d0a4f8acae71a583a6713cab5554e60b9bb8d27
+    version: 1.2.1
     source:
-      Path: hardware/deps/cluster_interconnect
+      Git: https://github.com/pulp-platform/cluster_interconnect.git
     dependencies:
     - common_cells
   common_cells:
-    revision: null
-    version: null
+    revision: 13f28aa0021fc22c0d01a12d618fda58d2c93239
+    version: 1.33.0
     source:
-      Path: hardware/deps/common_cells
+      Git: https://github.com/pulp-platform/common_cells.git
     dependencies:
     - common_verification
     - tech_cells_generic
   common_verification:
-    revision: null
-    version: null
+    revision: 9c07fa860593b2caabd9b5681740c25fac04b878
+    version: 0.2.3
     source:
-      Path: hardware/deps/common_verification
+      Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
   fpnew:
-    revision: null
+    revision: 9481d57c161bb160fd294eae07279082bff06698
     version: null
     source:
-      Path: hardware/deps/fpnew
+      Git: https://github.com/pulp-platform/cvfpu.git
     dependencies:
     - common_cells
     - fpu_div_sqrt_mvp
   fpu_div_sqrt_mvp:
-    revision: null
+    revision: 917dd79cb2dc1a8f43df1a84e0e4231508a980e9
     version: null
     source:
-      Path: hardware/deps/fpu_div_sqrt_mvp
+      Git: https://github.com/pulp-platform/fpu_div_sqrt_mvp.git
     dependencies:
     - common_cells
   idma:
@@ -72,10 +72,10 @@ packages:
     - common_verification
     - register_interface
   register_interface:
-    revision: null
-    version: null
+    revision: e25b36670ff7aab3402f40efcc2b11ee0f31cf19
+    version: 0.4.3
     source:
-      Path: hardware/deps/register_interface
+      Git: https://github.com/pulp-platform/register_interface.git
     dependencies:
     - apb
     - axi
@@ -104,9 +104,9 @@ packages:
     - axi
     - common_cells
   tech_cells_generic:
-    revision: null
-    version: null
+    revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf
+    version: 0.2.13
     source:
-      Path: hardware/deps/tech_cells_generic
+      Git: https://github.com/pulp-platform/tech_cells_generic.git
     dependencies:
     - common_verification

Bender.yml

@@ -14,12 +14,9 @@ dependencies:
   reqrsp_interface:     { path: "hardware/deps/reqrsp_interface"                                             }
   snitch:               { path: "hardware/deps/snitch"                                                       }
   tech_cells_generic:   { git: "https://github.com/pulp-platform/tech_cells_generic.git",   version: 0.2.13  }
-  fpnew:                { git: "https://github.com/pulp-platform/cvfpu.git",                rev: pulp-v0.1.3 }
+  fpnew:                { git: "https://github.com/pulp-platform/cvfpu.git",                rev: "9481d57"   }
   cluster_icache:       { git: "https://github.com/pulp-platform/cluster_icache.git",       version: 0.1.1   }
 
-workspace:
-  checkout_dir: "./hardware/deps"
-
 export_include_dirs:
   - hardware/include
 
@@ -48,6 +45,7 @@ sources:
   # Level 5
   - hardware/src/ctrl_registers.sv
   # Level 6
+  - hardware/src/tc_sram_simwrapper.sv
   - hardware/src/mempool_system.sv
 
   - target: mempool_vsim

CHANGELOG.md

@@ -43,6 +43,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 - Add fp8 microkernels: axpy, matmul, batchnorm, layernorm, softmax
 - Optimize fp16 matmul kernel
 - Add fall through register after LSU input
+- Benderize MemPool dependencies
 
 ### Fixed
 - Fix type issue in `snitch_addr_demux`