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[RISCV] Implement linker relaxation for R_RISCV_QC_ACCESS_16 and R_RISCV_QC_ACCESS_32#1142

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[RISCV] Implement linker relaxation for R_RISCV_QC_ACCESS_16 and R_RISCV_QC_ACCESS_32#1142
lenary wants to merge 4 commits into
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lenary:pr/riscv-qc-access-relax

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@lenary lenary commented May 7, 2026

Relaxes qc.e.li + load/store pairs annotated with R_RISCV_QC_ACCESS_32 (32-bit
instruction) or R_RISCV_QC_ACCESS_16 (16-bit compressed instruction). Four
relaxation variants are applied in priority order:

  1. GP-std: qc.e.li + ls → GP-relative 32-bit load/store (saves 6/4 bytes)
  2. Abs-std: qc.e.li + ls → x0-based 32-bit load/store (saves 6/4 bytes)
  3. GP-xqci: qc.e.li + ls → 6-byte qc.e.l*/qc.e.s* (saves 4/2 bytes)
  4. Abs-xqci: qc.e.li + ls → 6-byte qc.e.l*/qc.e.s* (saves 4/2 bytes)

All variants require --relax-xqci. The ACCESS relocation must carry
R_RISCV_RELAX for pair relaxation to occur; without it the qc.e.li falls
back to standalone relaxation. The ACCESS relocation must be exactly 6 bytes
after the qc.e.li.

New internal relocation types R_RISCV_QC_{ABS,GPREL}26_{I,S} are added for
the xqcilo immediate field, along with encoding types EncTy_QC_EI/EncTy_QC_ES
and their encode/clear helpers.

ELFSection::hasFollowing(R, Type) is added to check whether a relocation is
immediately followed by one of a given type in the section's relocation list.

--

Stacked on #1139

Assisted by Claude.

These QUALCOMM vendor relocations mark 16-bit compressed and 32-bit
load/store instructions as candidates for relaxation from a QC_E_LI +
Load/Store sequence.

This Change:
- Extends the internal QUALCOMM relocation range to cover the new
  relocations
- registers them with applyNone (marker semantics, no instruction
  changes),
- and add tests covering loads, stores, and compressed instructions.

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Signed-off-by: Sam Elliott <aelliott@qti.qualcomm.com>
@lenary

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…SCV_QC_ACCESS_32

Relaxes qc.e.li + load/store pairs annotated with R_RISCV_QC_ACCESS_32 (32-bit
instruction) or R_RISCV_QC_ACCESS_16 (16-bit compressed instruction). Four
relaxation variants are applied in priority order:

  1. GP-std:   qc.e.li + ls → GP-relative 32-bit load/store (saves 6/4 bytes)
  2. Abs-std:  qc.e.li + ls → x0-based 32-bit load/store (saves 6/4 bytes)
  3. GP-xqci:  qc.e.li + ls → 6-byte qc.e.l*/qc.e.s* (saves 4/2 bytes)
  4. Abs-xqci: qc.e.li + ls → 6-byte qc.e.l*/qc.e.s* (saves 4/2 bytes)

All variants require --relax-xqci. The ACCESS relocation must carry
R_RISCV_RELAX for pair relaxation to occur; without it the qc.e.li falls
back to standalone relaxation. The ACCESS relocation must be exactly 6 bytes
after the qc.e.li.

New internal relocation types R_RISCV_QC_{ABS,GPREL}26_{I,S} are added for
the xqcilo immediate field, along with encoding types EncTy_QC_EI/EncTy_QC_ES
and their encode/clear helpers.

ELFSection::hasFollowing(R, Type) is added to check whether a relocation is
immediately followed by one of a given type in the section's relocation list.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
Signed-off-by: Sam Elliott <aelliott@qti.qualcomm.com>
@lenary lenary force-pushed the pr/riscv-qc-access-relax branch from 9f0a6af to 76c9161 Compare May 7, 2026 17:19
lenary added 2 commits May 7, 2026 11:56
Signed-off-by: Sam Elliott <aelliott@qti.qualcomm.com>
Signed-off-by: Sam Elliott <aelliott@qti.qualcomm.com>
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