Promotes 5 Thumb-mode bare-metal Arm targets to Tier 2 by cezarbbb · Pull Request #155763 · rust-lang/rust

cezarbbb · 2026-04-25T03:43:22Z

This PR promotes five Thumb-mode bare-metal Arm targets to Tier 2, joining their Arm-mode counterparts which are already Tier 2:

Thumb-mode target (Tier 3 → Tier 2)	Arm-mode counterpart (already Tier 2)
`thumbv7a-none-eabi`	`armv7a-none-eabi`
`thumbv7a-none-eabihf`	`armv7a-none-eabihf`
`thumbv7r-none-eabi`	`armv7r-none-eabi`
`thumbv7r-none-eabihf`	`armv7r-none-eabihf`
`thumbv8r-none-eabihf`	`armv8r-none-eabihf`

Note: There is no thumbv8r-none-eabi target because the Cortex-R52 processor always includes an FPU, making a soft-float ABI variant unnecessary.

These Thumb-mode targets generate T32 code by default while their Arm-mode counterparts generate A32 code. They share the same LLVM backend, ABI, and data layout — the only spec differences are the llvm_target string and the description.

See rust-lang/compiler-team#985

rustbot · 2026-04-25T03:43:25Z

Some changes occurred in src/doc/rustc/src/platform-support

cc @Noratrieb

These commits modify compiler targets.
(See the Target Tier Policy.)

rustbot · 2026-04-25T03:43:27Z

r? @adwinwhite

rustbot has assigned @adwinwhite.
They will have a look at your PR within the next two weeks and either review your PR or reassign to another reviewer.

Use r? to explicitly pick a reviewer

Why was this reviewer chosen?

The reviewer was selected based on:

Owners of files modified in this PR: @ehuss, compiler
@ehuss, compiler expanded to 74 candidates
Random selection from 20 candidates

petrochenkov · 2026-04-27T15:20:17Z

Blocked on rust-lang/compiler-team#985.
@rustbot blocked

cezarbbb · 2026-04-28T12:33:45Z

@rustbot ping arm-maintainers
As the T32 and A32 targets share a page in the rustc book, can you continue to be the maintainers of these targets?

rustbot · 2026-04-28T12:33:48Z

Error: Only Rust team members can ping teams.

Please file an issue on GitHub at triagebot if there's a problem with this bot, or reach out on #triagebot on Zulip.

SparrowLii · 2026-04-28T12:35:40Z

@rustbot ping arm-maintainers
:)

rustbot · 2026-04-28T12:35:43Z

Error: This team (arm-maintainers) cannot be pinged via this command; it may need to be added to triagebot.toml on the default branch.

Please file an issue on GitHub at triagebot if there's a problem with this bot, or reach out on #triagebot on Zulip.

thejpster · 2026-05-02T16:29:56Z

arm-maintainers said yes over on rust-lang/compiler-team#985 (comment) (just for anyone else looking at this without looking at that thread first)

rustbot · 2026-05-30T01:27:38Z

This PR was rebased onto a different main commit. Here's a range-diff highlighting what actually changed.

Rebasing is a normal part of keeping PRs up to date, so no action is needed—this note is just to help reviewers.

cezarbbb · 2026-06-01T10:27:42Z

@petrochenkov The FCP is complete

petrochenkov · 2026-06-01T11:32:14Z

@bors r+

rust-bors · 2026-06-01T11:32:17Z

📌 Commit f45a817 has been approved by petrochenkov

It is now in the queue for this repository.

…=petrochenkov Promotes 5 Thumb-mode bare-metal Arm targets to Tier 2 This PR promotes five Thumb-mode bare-metal Arm targets to Tier 2, joining their Arm-mode counterparts which are already Tier 2: | Thumb-mode target (Tier 3 → Tier 2) | Arm-mode counterpart (already Tier 2) | |:---|:---| | `thumbv7a-none-eabi` | `armv7a-none-eabi` | | `thumbv7a-none-eabihf` | `armv7a-none-eabihf` | | `thumbv7r-none-eabi` | `armv7r-none-eabi` | | `thumbv7r-none-eabihf` | `armv7r-none-eabihf` | | `thumbv8r-none-eabihf` | `armv8r-none-eabihf` | Note: There is no `thumbv8r-none-eabi` target because the Cortex-R52 processor always includes an FPU, making a soft-float ABI variant unnecessary. These Thumb-mode targets generate T32 code by default while their Arm-mode counterparts generate A32 code. They share the same LLVM backend, ABI, and data layout — the only spec differences are the `llvm_target` string and the description. See rust-lang/compiler-team#985

cezarbbb · 2026-06-03T02:55:28Z

Hi. I found that cc-rs automatically adds three key flags for armv7r-none-eabihf: -marm / -march=armv7-r / -mfpu=vfpv3-d16 (see cc-rs/src/lib.rs:2476-2495), but the Thumb targets — thumbv7r-none-eabihf, thumbv7a-none-eabihf, thumbv8r-none-eabihf — don't match those branches. cc-rs only adds -mthumb for them, not -march or -mfpu.

ARM and Thumb differ only in instruction encoding; the underlying hardware requirements are identical. For example, armv7r_none_eabihf.rs:20 and thumbv7r_none_eabihf.rs:20 both specify +vfp3d16, and armv7a_none_eabihf.rs:20 and thumbv7a_none_eabihf.rs:20 both specify +vfp3d16,-neon,+strict-align. So they need the same -mfpu=vfpv3-d16. My approach is simply to replicate the FPU that cc-rs already selects for the ARM variants, written explicitly in the Thumb variants' Dockerfile CFLAGS.

For thumbv8r-none-eabihf's -mfpu=fp-armv8, I simply followed @thejpster's existing armv8r config in the Dockerfile. I also want to ask @thejpster, does these approaches above look correct to you?

cezarbbb · 2026-06-03T02:56:23Z

@rustbot ready

petrochenkov · 2026-06-03T06:28:22Z

Thanks!
@bors r+

rust-bors · 2026-06-03T06:28:24Z

📌 Commit e3468ae has been approved by petrochenkov

It is now in the queue for this repository.

🌲 The tree is currently closed for pull requests below priority 5. This pull request will be tested once the tree is reopened.

thejpster · 2026-06-03T06:39:22Z

Picking the same options as the existing Arm mode targets sounds right to me. You could build the targets and do a run of the rust-embedded/aarch32 suite to check, as it does a little bit of float maths.

…=petrochenkov Promotes 5 Thumb-mode bare-metal Arm targets to Tier 2 This PR promotes five Thumb-mode bare-metal Arm targets to Tier 2, joining their Arm-mode counterparts which are already Tier 2: | Thumb-mode target (Tier 3 → Tier 2) | Arm-mode counterpart (already Tier 2) | |:---|:---| | `thumbv7a-none-eabi` | `armv7a-none-eabi` | | `thumbv7a-none-eabihf` | `armv7a-none-eabihf` | | `thumbv7r-none-eabi` | `armv7r-none-eabi` | | `thumbv7r-none-eabihf` | `armv7r-none-eabihf` | | `thumbv8r-none-eabihf` | `armv8r-none-eabihf` | Note: There is no `thumbv8r-none-eabi` target because the Cortex-R52 processor always includes an FPU, making a soft-float ABI variant unnecessary. These Thumb-mode targets generate T32 code by default while their Arm-mode counterparts generate A32 code. They share the same LLVM backend, ABI, and data layout — the only spec differences are the `llvm_target` string and the description. See rust-lang/compiler-team#985

Rollup of 7 pull requests Successful merges: - #155763 (Promotes 5 Thumb-mode bare-metal Arm targets to Tier 2) - #156928 (Remove -Zemscripten-wasm-eh) - #157236 (Reorganize `tests/ui/issues` [3/N]) - #157294 (Split coroutine layout computation to its own file) - #157328 (windows: Elide division-by-zero checks in Instant::now()) - #157331 (Rewrite target checking for `#[link]`) - #157336 (Enable `clippy::mem_replace_with_default`)

rust-bors · 2026-06-03T09:26:57Z

⌛ Testing commit e3468ae with merge e8def2b...

Workflow: https://github.com/rust-lang/rust/actions/runs/26875909522

Promotes 5 Thumb-mode bare-metal Arm targets to Tier 2 This PR promotes five Thumb-mode bare-metal Arm targets to Tier 2, joining their Arm-mode counterparts which are already Tier 2: | Thumb-mode target (Tier 3 → Tier 2) | Arm-mode counterpart (already Tier 2) | |:---|:---| | `thumbv7a-none-eabi` | `armv7a-none-eabi` | | `thumbv7a-none-eabihf` | `armv7a-none-eabihf` | | `thumbv7r-none-eabi` | `armv7r-none-eabi` | | `thumbv7r-none-eabihf` | `armv7r-none-eabihf` | | `thumbv8r-none-eabihf` | `armv8r-none-eabihf` | Note: There is no `thumbv8r-none-eabi` target because the Cortex-R52 processor always includes an FPU, making a soft-float ABI variant unnecessary. These Thumb-mode targets generate T32 code by default while their Arm-mode counterparts generate A32 code. They share the same LLVM backend, ABI, and data layout — the only spec differences are the `llvm_target` string and the description. See rust-lang/compiler-team#985

JonathanBrouwer · 2026-06-03T09:28:53Z

@bors yield

rust-bors · 2026-06-03T09:28:56Z

Auto build was cancelled. Cancelled workflows:

https://github.com/rust-lang/rust/actions/runs/26875909522

The next pull request likely to be tested is #157349.

…=petrochenkov Promotes 5 Thumb-mode bare-metal Arm targets to Tier 2 This PR promotes five Thumb-mode bare-metal Arm targets to Tier 2, joining their Arm-mode counterparts which are already Tier 2: | Thumb-mode target (Tier 3 → Tier 2) | Arm-mode counterpart (already Tier 2) | |:---|:---| | `thumbv7a-none-eabi` | `armv7a-none-eabi` | | `thumbv7a-none-eabihf` | `armv7a-none-eabihf` | | `thumbv7r-none-eabi` | `armv7r-none-eabi` | | `thumbv7r-none-eabihf` | `armv7r-none-eabihf` | | `thumbv8r-none-eabihf` | `armv8r-none-eabihf` | Note: There is no `thumbv8r-none-eabi` target because the Cortex-R52 processor always includes an FPU, making a soft-float ABI variant unnecessary. These Thumb-mode targets generate T32 code by default while their Arm-mode counterparts generate A32 code. They share the same LLVM backend, ABI, and data layout — the only spec differences are the `llvm_target` string and the description. See rust-lang/compiler-team#985

…uwer Rollup of 15 pull requests Successful merges: - #155763 (Promotes 5 Thumb-mode bare-metal Arm targets to Tier 2) - #156953 (delegation: emit error when there is an infer lifetime in user-specified args) - #157248 (delegation: move statements out of the first arg) - #157263 (rustc_codegen_ssa: Refactor `ArchiveEntry` to include entry kind) - #157311 (Use weak linkage for EII defaults) - #156089 (Fix unused_parens for pinned reference patterns) - #156928 (Remove -Zemscripten-wasm-eh) - #157236 (Reorganize `tests/ui/issues` [3/N]) - #157287 (Const generics: remove AliasTerm::kind(), and small fixes) - #157294 (Split coroutine layout computation to its own file) - #157328 (windows: Elide division-by-zero checks in Instant::now()) - #157331 (Rewrite target checking for `#[link]`) - #157336 (Enable `clippy::mem_replace_with_default`) - #157362 (Fix trivial wf module argument/doc comment name mismatches) - #157364 (Rewrite target checking of `rustc_dummy`) Failed merges: - #157332 (Rewrite target checking for `#[sanitize]`)

Rollup merge of #155763 - cezarbbb:promote-thumb-to-tier2, r=petrochenkov Promotes 5 Thumb-mode bare-metal Arm targets to Tier 2 This PR promotes five Thumb-mode bare-metal Arm targets to Tier 2, joining their Arm-mode counterparts which are already Tier 2: | Thumb-mode target (Tier 3 → Tier 2) | Arm-mode counterpart (already Tier 2) | |:---|:---| | `thumbv7a-none-eabi` | `armv7a-none-eabi` | | `thumbv7a-none-eabihf` | `armv7a-none-eabihf` | | `thumbv7r-none-eabi` | `armv7r-none-eabi` | | `thumbv7r-none-eabihf` | `armv7r-none-eabihf` | | `thumbv8r-none-eabihf` | `armv8r-none-eabihf` | Note: There is no `thumbv8r-none-eabi` target because the Cortex-R52 processor always includes an FPU, making a soft-float ABI variant unnecessary. These Thumb-mode targets generate T32 code by default while their Arm-mode counterparts generate A32 code. They share the same LLVM backend, ABI, and data layout — the only spec differences are the `llvm_target` string and the description. See rust-lang/compiler-team#985

jonathanpallant · 2026-06-04T08:48:40Z

New rustup targets seem to run the aarch32 test suite without issue (rust-embedded/aarch32#174).

rustbot added S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. T-compiler Relevant to the compiler team, which will review and decide on the PR/issue. labels Apr 25, 2026

rustbot assigned adwinwhite Apr 25, 2026

cezarbbb mentioned this pull request Apr 25, 2026

Promotes 5 Thumb-mode bare-metal Arm targets to Tier 2 rust-lang/compiler-team#985

Open

3 tasks

petrochenkov self-assigned this Apr 27, 2026

rustbot added S-blocked Status: Blocked on something else such as an RFC or other implementation work. and removed S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. labels Apr 27, 2026

petrochenkov unassigned adwinwhite Apr 27, 2026

cezarbbb force-pushed the promote-thumb-to-tier2 branch from 0b1bacb to f45a817 Compare May 30, 2026 01:27

rustbot added A-CI Area: Our Github Actions CI A-testsuite Area: The testsuite used to check the correctness of rustc T-infra Relevant to the infrastructure team, which will review and decide on the PR/issue. labels May 30, 2026

petrochenkov added S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. and removed S-blocked Status: Blocked on something else such as an RFC or other implementation work. labels Jun 1, 2026

rust-bors Bot added S-waiting-on-bors Status: Waiting on bors to run and complete tests. Bors will change the label on completion. and removed S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. labels Jun 1, 2026

JonathanBrouwer mentioned this pull request Jun 1, 2026

Rollup of 10 pull requests #157246

Closed

petrochenkov added S-waiting-on-author Status: This is awaiting some action (such as code changes or more information) from the author. and removed S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. labels Jun 2, 2026

rustbot added S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. and removed S-waiting-on-author Status: This is awaiting some action (such as code changes or more information) from the author. labels Jun 3, 2026

rust-bors Bot added S-waiting-on-bors Status: Waiting on bors to run and complete tests. Bors will change the label on completion. and removed S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. labels Jun 3, 2026

jhpratt mentioned this pull request Jun 3, 2026

Rollup of 7 pull requests #157361

Closed

JonathanBrouwer mentioned this pull request Jun 3, 2026

Rollup of 9 pull requests #157372

Closed

This was referenced Jun 3, 2026

Rollup of 15 pull requests #157375

Closed

Rollup of 15 pull requests #157376

Merged

rust-bors Bot merged commit bc3903e into rust-lang:main Jun 3, 2026
13 of 14 checks passed

rustbot added this to the 1.98.0 milestone Jun 3, 2026

cezarbbb deleted the promote-thumb-to-tier2 branch June 3, 2026 16:30

jonathanpallant mentioned this pull request Jun 4, 2026

New thumb targets at Tier 2 rust-embedded/aarch32#172

Closed

Uh oh!

Conversation

cezarbbb commented Apr 25, 2026 • edited by rustbot Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

rustbot commented Apr 25, 2026

Uh oh!

rustbot commented Apr 25, 2026

Uh oh!

petrochenkov commented Apr 27, 2026

Uh oh!

cezarbbb commented Apr 28, 2026

Uh oh!

rustbot commented Apr 28, 2026

Uh oh!

SparrowLii commented Apr 28, 2026

Uh oh!

rustbot commented Apr 28, 2026

Uh oh!

thejpster commented May 2, 2026

Uh oh!

rustbot commented May 30, 2026

Uh oh!

cezarbbb commented Jun 1, 2026

Uh oh!

petrochenkov commented Jun 1, 2026

Uh oh!

rust-bors Bot commented Jun 1, 2026

Uh oh!

cezarbbb commented Jun 3, 2026 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

cezarbbb commented Jun 3, 2026

Uh oh!

petrochenkov commented Jun 3, 2026

Uh oh!

rust-bors Bot commented Jun 3, 2026

Uh oh!

thejpster commented Jun 3, 2026

Uh oh!

rust-bors Bot commented Jun 3, 2026 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

JonathanBrouwer commented Jun 3, 2026

Uh oh!

rust-bors Bot commented Jun 3, 2026

Uh oh!

Uh oh!

jonathanpallant commented Jun 4, 2026

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

9 participants

cezarbbb commented Apr 25, 2026 •

edited by rustbot

Loading

cezarbbb commented Jun 3, 2026 •

edited

Loading

rust-bors Bot commented Jun 3, 2026 •

edited

Loading