Generates an ASIC PG grid model from YAML + ITF inputs:
output/pg_grid_netlist.sp(SPICE RC + instances +.MEAS)output/pg_grid_visualization.html(2D grid + stack cross-section)output/pg_grid_summary.txt(ASCII report)
- Live demo: https://smprather.github.io/pg-grid-netlist-gen
- Configuration documentation:
docs/configuration.md
- Python
>=3.14 uv(recommended)
uv pip install -e .uv pip install -e ../pg_grid_netlist_gen config.yaml.\.venv\Scripts\pg-grid-netlist-gen.exe config.yamlOr use the batch script wrapper:
.\pg-grid-netlist-gen.bat config.yamlCommon options (all platforms):
./pg_grid_netlist_gen config.yaml --open-browser
./pg_grid_netlist_gen config.yaml --output-dir outputOr on Windows:
.\.venv\Scripts\pg-grid-netlist-gen.exe config.yaml --open-browser
.\.venv\Scripts\pg-grid-netlist-gen.exe config.yaml --output-dir outputPrimary inputs:
config.yaml- ITF file referenced by
itf.file(for examplefreepdk3_rctyp.itf)
Highlights:
- Grid layer usage supports stripe (
grid) and staple (staple) layers. - Metal resistance uses ITF
RPSQ. - Via resistance uses ITF
RPV. - Standard-cell PG pins tap directly onto lowest metal grid nodes by pin
type(power/ground), not by pin name. - IR-drop measurements are generated for both output rise and output fall per instance, with edge mapping based on
standard_cells[].unateness. - Optional external cell model include:
standard_cells[].spice_netlist_file. - Netlist includes HSPICE probing for instance pin voltages via
.PROBE V(X*).
This repo includes a versioned pre-commit hook at:
.githooks/pre-commit
It regenerates outputs from config.yaml and stages output/ artifacts before each commit.
Enable it once per clone:
git config core.hooksPath .githooks- Default outputs are written under
output/. - The HTML visualization uses legend toggles for layers (no dropdown selector).
- The cross-section plot is included below the 2D grid view.