Use AI to build optimal Inference Compute systems
Run the standard-library tests locally:
python3 -m unittest discover -s dv/tests -vThis includes the Phase 8 firmware/driver suite: freestanding C compilation, MMIO boot simulation, secure-boot negative paths, graph submission, KV fault replay, and telemetry validation.
Run the first event-model simulation:
python3 -m sim.event_model.rcif_sim sim/workloads/sample_agentic_coding_trace.json --prettyGenerate a synthetic agentic coding trace:
python3 -m sim.tracegen.generate_agentic_trace \
--requests 4 \
--prefix-tokens 131072 \
--reuse-ratio 0.9 \
--output /tmp/generated_agentic_trace.jsonVerilator lint/build/simulation runs on Modal CPU workers by default. Local Verilator is not required.
make lint
make verilate
make sim
make regress
make phase9
make phase10If modal is not on PATH:
MODAL=/Users/kb/Library/Python/3.9/bin/modal make regressThe local-* targets are only for debugging on machines that already have Verilator installed:
make local-lint
make local-sim
make local-regress
make local-phase9phase9 adds assertion-enabled full-chip directed and randomized simulation,
security/memory-safety invariant tests, real descriptor-trace replay, exhaustive
cross coverage, reset/backpressure stress, and an enforced Verilator coverage
report. See the full-chip verification plan
for bounded scope and physical-signoff gates.
phase10 adds the reduced FPGA shell, an AXI external-DDR proxy, real runtime
token-graph submission, a bit-exact toy attention/GEMV block, synthetic agentic
trace replay, KV page-fault migration, and a 5% cycle-model agreement gate. See
the FPGA prototype guide for the reproducible emulation scope
and the physical-board closure requirements.
The current cloud verification record is Modal RTL Verification Record — 2026-07-21. It records passing subsystem regression, Phase 9 full-chip coverage, and Phase 10 FPGA-shell/DDR simulation runs, including the exact tool revision and Modal run IDs.