Add register read-port constraint validation for direct routing bypass#275
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guosran wants to merge 2 commits intotancheng:masterfrom
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Add register read-port constraint validation for direct routing bypass#275guosran wants to merge 2 commits intotancheng:masterfrom
guosran wants to merge 2 commits intotancheng:masterfrom
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… bypass Implement hardware constraint validation in the mapping/compilation phase to ensure correct control word generation for the new register → routing_crossbar direct data path (VectorCGRA feature). Key changes: - Identify routing bypass operations (REG → PORT MOV/DATA_MOV) - Enforce single read-port constraint: if computation and routing bypass both read from the same register cluster in same time step, they MUST read the identical register index - Two-pass processing: FU-bound operations first, then routing bypass operations with constraint validation - Support instructions with only routing operations (no FU involvement) - Thread num_tile_inports parameter through mapper for flexible tile configs - Restore and improve comments with third-person-singular verb form Validation tested with: - Direct constraint violation/acceptance tests - Routing bypass with standalone and mixed operations - Full module import and pytest collection Made-with: Cursor
tancheng
reviewed
Mar 17, 2026
| return 'IMM' | ||
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| def _is_take_up_fu_operation(operation): | ||
| if operation['opcode'] == 'MOV' or operation['opcode'] == 'DATA_MOV': |
Owner
There was a problem hiding this comment.
I actually doubt about this _is_take_up_fu_operation() func. I thought all operations except mov should take up fu. mov shouldn't be "operation". So in summary, I thought this func should be:
def _is_take_up_fu_operation(operation):
if operation['opcode'] == 'MOV' or operation['opcode'] == 'DATA_MOV':
return False
return True
CCing @Jackcuii.
Owner
|
Hi @guosran, coredac/neura#283 is for fixing the mapper in dataflow compiler, instead of this VectorCGRA repo. Do you think we also need to refine this script? |
Collaborator
Author
Sorry my bad... |
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Summary
This PR addresses coredac/neura#283. It validates hardware constraint during mapping: if computation and routing bypass both read from the same register cluster in the same time step, they must read the identical register index.
Changes
_is_reg_to_outport_routing(): identifies REG→PORT routing operations_is_take_up_fu_operation(): returns False for MOV with PORT destinations only