M7d: symmetry storage halving — ceil(L/2) stored rows, mirrored dots

[tap]

⚠️ Merge order

This PR bumps the DspTap submodule pin to the dot_row_reversed commit — merge DspTap #6 first so the pinned commit is reachable from its main.

What

Lever 3 of the M7 campaign, in two PRs per the substrate discipline (kernel in DspTap first, consumer here).

The linear-phase prototype satisfies b_p[t] = b_{L−1−p}[T−1−t] — branch p is branch L−1−p tap-reversed. So:

• basic_phase_table now stores only ⌈L/2⌉ rows (74 of 147 down, 80 of 160 up; odd L keeps its self-symmetric middle branch as a stored row). A mirrored phase dots its partner's stored row backward via tap::dsp::dot_row_reversed — same products, same accumulation order, bit-identical outputs to a full table.
• Quantization is canonical over the stored half, so the mirror is exact by construction, and the fixed-point exact-unity row sums carry over (reversal preserves the coefficient multiset).
• Storage, pinned by test: economy f32 44.8 → 22.5 KiB (down), 27.5 → 13.8 KiB (up); transparent 105.7 → 53.2 / 60.0 → 30.0 KiB; Q15 halves those again.
• The every-phase table battery now runs through the same stored_row/is_mirrored pairing the hot path uses, plus an exhaustive mirror-identity sweep (every phase × every tap).

The part the ratchet earned

First measurement: M55 up_q15 +3.3% REGRESSION. Diagnostics isolated it — a build with both arms calling the forward kernel cost the same, so the reversed kernel is free and the second inlined dot expansion in the walk's loop body is what broke Arm's unrolled codegen. Outlining the mirrored arm fixed Arm — and regressed Hexagon (down_q31 +3.3% called vs +2.7% inlined: hexagon-clang keeps both expansions tight and pays for the call instead). So the mirrored-arm out-lining is gated per target (TAP_RATIO_MIRRORED_DOT_ATTR), the same measured-per-target pattern as the tap::dsp kernel gates.

Final result: zero baseline changes on all three targets — the halving is compute-free within the ±3% gate. Worst residual: Hexagon down_q31 +2.7% (rides as slack); Arm came out slightly ahead (M33 Q31 −2.5%, M55 up_q15 −1.1%).

Verification

• 58/58 host (gcc and clang -Werror); scipy vectors, pull-parity, custom-taps impulse all bit-exact.
• M55 and M33 bare-metal suites green — the M33 leg is the on-target bit-exactness proof of DspTap's SMLALDX swapped-lane pairing (the impulse-reproduces-table sweep hits every mirrored phase with the intrinsic active).
• Hexagon 56/56 under emulation; bluetooth_bridge identical; clang-tidy clean.
• PLAN §4 storage table + §7 lever entry updated.

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https://claude.ai/code/session_01Ldeq57sBySx2nFTQsGcQB6

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