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v0.2: wrap the M7 codegen campaign - #11

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claude/v0.2-wrap
Jul 24, 2026
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v0.2: wrap the M7 codegen campaign#11
tap merged 1 commit into
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claude/v0.2-wrap

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@tap tap commented Jul 24, 2026

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What

Declares the output-preserving phase of the M7 optimization campaign complete and bumps the version to 0.2.0 (CMake project + TAP_RATIO_VERSION_*). Docs-and-version only — no engine changes, no baseline changes.

What v0.2 contains (all previously merged, each measured by the ratchet, outputs bit-identical throughout):

  • M7a — the measurement harness: embedded CI matrix (M33/M55/Hexagon under QEMU) + the two-sided ±3% instruction-count ratchet.
  • M7b — the superblock walk.
  • M7c — committed compile-time trip counts.
  • M7d — symmetry-halved tables (with the dot_row_reversed kernel in DspTap).

Cumulative vs the M7a baselines: M55 Q15 −59%/−60% and float −35%/−37%; M33 Q31 −26%/−27%, Q15 −15%/−16%; Hexagon Q15 −13%/−10%, Q31 −15%/−7%; table storage halved (economy Q15 up: 6.9 KiB).

README and PLAN now record the deferral rationale for the remaining §7 levers (multistage, minimum-phase, IIR pre-filter, FFT offline): each changes the output contract or serves a currently-unpressured need, so they wait for a consumer to pull them — a latency need pulls minimum-phase, a storage need pulls multistage, an MCU float consumer pulls the accumulation-contract discussion in DspTap.

Suggest tagging v0.2.0 on the merge commit.

Verification

58/58 host suite green; version bump asserted nowhere (checked), so no test churn.

🤖 Generated with Claude Code

https://claude.ai/code/session_01Ldeq57sBySx2nFTQsGcQB6


Generated by Claude Code

Declares the output-preserving phase of the optimization campaign
complete and bumps the version (CMake project + TAP_RATIO_VERSION_*).
Four levers landed, each measured by the instruction-count ratchet,
outputs bit-identical throughout: the M7a harness itself, the M7b
superblock walk, the M7c committed trip counts, and the M7d
symmetry-halved tables. Cumulative vs the M7a baselines: M55 Q15
-59%/-60% and float -35%/-37%; M33 Q31 -26%/-27%, Q15 -15%/-16%;
Hexagon Q15 -13%/-10%, Q31 -15%/-7%; table storage halved (economy Q15
up: 6.9 KiB).

README and PLAN now state the deferral rationale for the remaining
levers (multistage, minimum-phase, IIR pre-filter, FFT offline): each
changes the output contract or serves a currently-unpressured need, so
they wait for a consumer to pull them — a latency need pulls
minimum-phase, a storage need pulls multistage, an MCU float consumer
pulls the accumulation-contract discussion in DspTap.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01Ldeq57sBySx2nFTQsGcQB6
@tap
tap merged commit 9f871b5 into main Jul 24, 2026
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2 participants