Laboratory exercises on digital circuit testing using Atalanta & HOPE (ATPG and fault simulation) and Synopsys tools (Design Compiler & TetraMax).

VLSI laboratory design report covering CMOS circuits, simulation, and physical verification.

Verilog implementations and simulations for a Digital Logic Design I course, including combinational circuits, hierarchical design, multiplexers, comparators, and BCD arithmetic with timing analysis.

Solved exercises and handwritten study notes for the Quantum Modular Systems course, covering entanglement, measurements, Bell states, and quantum communication protocols.

Laboratory exercises for the course CAD for Digital Hardware (E-CAD), covering graphical digital design, PCB back-end flow, and HDL-based FPGA implementation using VHDL, ModelSim, and Vivado on the Basys3 (Artix-7) board.

Embedded systems course project focused on system-level design, with plans for future hands-on implementation in embedded C.