OpenTitan Flash Ctrl IP block

System Reset Controller (sysrst_ctrl) that provides programmable hardware-level responses to trusted IOs and basic board-level reset sequencing capabilities

Cryptographically Secure Random Number Generator (CSRNG)

This document specifies the OTP MACRO hardware IP functionality.

The mailbox IP block in the OpenTitan Integrated design implements a request-response channel that the host System-on-Chip (SoC) may use to request security ser

SRAM memory controller

OpenTitan Rv Core Ibex IP block

Entropy Distribution Network (EDN) interfaces to the CSRNG IP module

Keccak Message Authentication Code (KMAC) and Secure Hashing Algorithm 3 (SHA3)

ROM controller (rom_ctrl) is the connection between the chip and its ROM

RISC-V Debug System wrapper functionality

Entropy Source: interface to an external physical random noise generator

Analog to Digital Converter Control Interface

RISC-V timer module provides a configurable number of 64-bit counters

TL-UL is a lightweight (uncached) bus that combines the point-to-point split-transaction features of the powerful TileLink (or AMBA AXI) 5-channel bus without the high pin-count overhead.

OpenTitan Prim Xilinx Ultrascale IP block

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OpenTitan Prim Xilinx IP block

Debugging in RISC-V can be done using one of the following mechanisms:

The Direct Memory Access (DMA) controller is a peripheral within the OpenTitan system-on-chip (SoC).