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triple-modular-redundancy

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StackedArchitect / Fault-Tolerant-RISCV

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A fault-tolerant, pipelined RISC-V processor system implemented in Verilog, featuring Triple Modular Redundancy (TMR), SECDED memory protection, error injection, and robust recovery mechanisms. Designed for research, education, and prototyping of reliable digital systems.

fpga fault-tolerance riscv verilog computer-architecture error-detection-correction triple-modular-redundancy secded pipelined-processor
  • Updated Jun 26, 2025
  • Verilog

Gregory-Matthews / Dependable-Computing

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Graduate Level - Fundamental design issues involved in building reliable, safety-critical, and highly available systems. Topics include testing and fault-tolerant design of VLSI circuits, hardware and software fault tolerance, information redundancy, and fault-tolerant distributed systems.

markov-model fault-tolerance safety-critical tmr triple-modular-redundancy vlsi-circuits information-redundancy
  • Updated Dec 1, 2017
  • MATLAB

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