feat: specialized linear layout for decoupling capacitor partitions

[voltrace-io]

Summary

Replaces the generic PackSolver2 with a dedicated horizontal row layout for partitions of type decoupling_caps in SingleInnerPartitionPackingSolver.

Before: Decoupling capacitors are packed using the generic algorithm, which produces cluttered/chaotic arrangements.

After: Decoupling capacitors are arranged in a clean horizontal row:

[C7] [C8] [C9] [C10] [C11]
       ← centered at x=0 →

Implementation

Only one source file changed — SingleInnerPartitionPackingSolver.ts:

• When partitionType === "decoupling_caps", the solver uses layoutDecouplingCapsLinear() instead of PackSolver2
• Caps are sorted by chipId (lexicographic) for deterministic output
• The row is centered at x=0, y=0
• Respects decouplingCapsGap (falls back to chipGap, then 0.2)
• All caps get ccwRotationDegrees=0 (upright orientation)
• Existing PackSolver2 path unchanged for non-decoupling partitions

Tests

6 new tests added, all passing:

• Caps placed in horizontal row at y=0
• Deterministic sort by chipId
• Row centered at x=0
• Gap between adjacent caps matches decouplingCapsGap
• Single cap placed at origin
• All caps have rotation=0

Full suite: 23 pass, 1 skip, 0 new failures.

Addresses #15

/claim #15

Review & Testing Checklist for Human

• Verify the linear layout produces a cleaner arrangement than the default PackSolver2 for decoupling caps
• Verify non-decoupling partitions still use the original PackSolver2 path
• Run bun test — all tests should pass (23 pass, 1 skip; the pre-existing IdentifyDecouplingCapsSolver06 error is from circuit-to-svg)

Notes

• The pre-existing test failure in IdentifyDecouplingCapsSolver06.test.ts is caused by a missing export in circuit-to-svg and exists on main — not related to this PR.
• Only 2 files changed: 1 source file + 1 test file.

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