Unify Port and Bundle by merging Bundle functionality into Ports#453
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Unify Port and Bundle by merging Bundle functionality into Ports#453
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Pull request overview
This PR advances the “unify Port and Bundle” refactor by folding Bundle’s structural behavior into Port across the Python DSL, compiler, and IR schema/proto layer, while keeping a deprecated Bundle class for source compatibility.
Changes:
- Removes
Bundlefrom the protobuf IR (schema + elem), adds nestedportstoPort, and bumps the proto version to 8. - Refactors Python models and utilities to use
Port[...]instead ofBundle[...], including a private initializer-clone helper. - Refactors the Scala compiler/WIR to treat container ports as
elem.Port(removingIrPortwrapper and bundle-specific paths).
Reviewed changes
Copilot reviewed 55 out of 56 changed files in this pull request and generated 4 comments.
Show a summary per file
| File | Description |
|---|---|
| proto/edgir/schema.proto | Drops bundle from library namespace values (port-like unification). |
| proto/edgir/elem.proto | Adds ports to Port, removes Bundle and bundle branch from PortLike. |
| proto/README.md | Adds grpcio-tools to proto build instructions. |
| edg/parts/Jacdac.py | Migrates Jacdac ports from Bundle to Port. |
| edg/hdl_server/main.py | Bumps EDG_PROTO_VERSION and removes bundle proto emission. |
| edg/electronics_model/UsbPort.py | Migrates USB ports from Bundle to Port. |
| edg/electronics_model/UartPort.py | Migrates UART port from Bundle to Port. |
| edg/electronics_model/SpiPort.py | Migrates SPI ports from Bundle to Port. |
| edg/electronics_model/SpeakerPort.py | Migrates speaker ports from Bundle to Port. |
| edg/electronics_model/PinAssignmentUtil.py | Updates leaf-port flattening to treat container ports as Port. |
| edg/electronics_model/NetlistGenerator.py | Updates bundle connection logic to work with nested Port.ports. |
| edg/electronics_model/KiCadSchematicBlock.py | Treats navigable container ports as Port instead of Bundle. |
| edg/electronics_model/I2sPort.py | Migrates I2S ports from Bundle to Port. |
| edg/electronics_model/I2cPort.py | Migrates I2C ports from Bundle to Port. |
| edg/electronics_model/DvpPort.py | Migrates DVP ports from Bundle to Port. |
| edg/electronics_model/DebugPorts.py | Migrates debug ports from Bundle to Port. |
| edg/electronics_model/CrystalPort.py | Migrates crystal ports from Bundle to Port. |
| edg/electronics_model/CanPort.py | Migrates CAN ports from Bundle to Port. |
| edg/edgrpc/hdl_pb2.pyi | Regenerated stubs for updated proto version/schema. |
| edg/edgrpc/hdl_pb2.py | Regenerated protobuf runtime for updated schema. |
| edg/edgrpc/compiler_pb2.pyi | Regenerated stubs for updated proto version/schema. |
| edg/edgrpc/compiler_pb2.py | Regenerated protobuf runtime for updated schema. |
| edg/edgir/schema_pb2.pyi | Regenerated IR stubs after removing bundle from schema. |
| edg/edgir/schema_pb2.py | Regenerated IR runtime after removing bundle from schema. |
| edg/edgir/ref_pb2.pyi | Regenerated stubs (tooling update). |
| edg/edgir/ref_pb2.py | Regenerated runtime (tooling update). |
| edg/edgir/name_pb2.pyi | Regenerated stubs (tooling update). |
| edg/edgir/name_pb2.py | Regenerated runtime (tooling update). |
| edg/edgir/lit_pb2.pyi | Regenerated stubs (tooling update). |
| edg/edgir/lit_pb2.py | Regenerated runtime (tooling update). |
| edg/edgir/init_pb2.pyi | Regenerated stubs (tooling update). |
| edg/edgir/init_pb2.py | Regenerated runtime (tooling update). |
| edg/edgir/impl_pb2.pyi | Regenerated stubs (tooling update). |
| edg/edgir/impl_pb2.py | Regenerated runtime (tooling update). |
| edg/edgir/expr_pb2.py | Regenerated runtime (tooling update). |
| edg/edgir/elem_pb2.py | Regenerated runtime after Port structural changes / bundle removal. |
| edg/edgir/common_pb2.pyi | Regenerated stubs (tooling update). |
| edg/edgir/common_pb2.py | Regenerated runtime (tooling update). |
| edg/edgir/init.py | Removes Bundle exports and updates resolve_portlike / PortTypes. |
| edg/core/test_simple_const_prop.py | Updates test port class from Bundle to Port. |
| edg/core/test_inner_link.py | Updates test port classes from Bundle to Port. |
| edg/core/test_bundle.py | Updates bundle test to be Port-based. |
| edg/core/Util.py | Treats Port as the container port type for dict export. |
| edg/core/TransformUtil.py | Traversal now descends into edgir.Port.ports. |
| edg/core/Ports.py | Moves container-port behavior into Port, adds deprecated Bundle. |
| edg/core/Array.py | Removes BaseContainerPort usage and updates vector base type. |
| edg/abstract_parts/PinMappable.py | Switches pinmap resource models from Bundle to Port and uses private initializer helper. |
| edg/abstract_parts/IoController.py | Removes explicit Bundle branches (bundle is now a port). |
| compiler/src/test/scala/edg/wir/LibraryConnectivityAnalysisTest.scala | Updates test fixture from Port.Bundle to Port.Port. |
| compiler/src/test/scala/edg/compiler/CompilerLinkPortArrayExpansionTest.scala | Updates test fixtures to use Port.Port for container ports. |
| compiler/src/test/scala/edg/compiler/CompilerBundleExpansionTest.scala | Updates bundle-expansion tests to container Port. |
| compiler/src/main/scala/edg/wir/PortLike.scala | Removes bundle WIR type and makes Port mutable/recursive. |
| compiler/src/main/scala/edg/wir/Library.scala | Changes port retrieval/storage to elem.Port (no IrPort). |
| compiler/src/main/scala/edg/wir/BlockConnectivityAnalysis.scala | Removes bundle case from port-like type extraction. |
| compiler/src/main/scala/edg/compiler/PythonInterface.scala | Updates library API to return elem.Port only. |
| compiler/src/main/scala/edg/compiler/DesignStructuralValidate.scala | Updates port mapping signature to include child-port results. |
| compiler/src/main/scala/edg/compiler/DesignRefsValidate.scala | Updates port mapping signature to include child-port results. |
| compiler/src/main/scala/edg/compiler/DesignMap.scala | Removes bundle mapping, makes port mapping recursive via Port.ports. |
| compiler/src/main/scala/edg/compiler/DesignAssertionCheck.scala | Updates port mapping signature to match DesignMap. |
| compiler/src/main/scala/edg/compiler/Compiler.scala | Bumps expected proto version and removes bundle-specific logic. |
| compiler/src/main/scala/edg/Wrappers.scala | Deletes IrPort wrapper type (no longer needed). |
| compiler/src/main/scala/edg/ElemBuilder.scala | Collapses bundle builder into container Port builder and removes bundle library entries. |
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| @@ -237,7 +237,6 @@ def connect_ports( | |||
| (elt1[0].append_port(key), edgir.resolve_portlike(edgir.pair_get(elt1[1].ports, key))), | |||
| (elt2[0].append_port(key), edgir.resolve_portlike(edgir.pair_get(elt2[1].ports, key))), | |||
| ) | |||
edg/core/Ports.py
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| param._populate_decl_proto(edgir.add_pair(pb.params, name)) | ||
| for name, port in self._ports.items(): | ||
| port._populate_portlike_proto(edgir.add_pair(pb.ports, name)) | ||
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|
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| def leaf_circuit_ports(prefix: str, port: Port) -> Iterable[Tuple[str, CircuitPort]]: | ||
| if isinstance(port, CircuitPort): | ||
| return [(prefix, port)] | ||
| elif isinstance(port, Bundle): | ||
| return chain(*[leaf_circuit_ports(f"{prefix}.{name}", port) for (name, port) in port._ports.items()]) | ||
| else: | ||
| raise ValueError(f"unable to flatten {port}") | ||
| return chain(*[leaf_circuit_ports(f"{prefix}.{name}", port) for (name, port) in port._ports.items()]) |
| T = TypeVar("T", bound=Port) | ||
| T = TypeVar("T", bound="Port") | ||
|
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||
| def Port(self, tpe: T, *, desc: Optional[str] = None) -> T: |
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On the path to compositional passive. Also simplifies a bunch of code.
Refactors the libraries to use Port instead of Bundle, but retains Bundle with a deprecation warning.
Changes Bundle.with_elt_initializers to be private. It is an API with only one consumer in the pinmap util and a better solution will need to be found for it.
Updates the proto version.