Unify Port and Bundle by merging Bundle functionality into Ports

compiler/src/main/scala/edg/ElemBuilder.scala

@@ -219,33 +219,18 @@ object ElemBuilder {
     )
 
     def Port(
-        selfClass: String,
-        params: SeqMap[String, init.ValInit] = SeqMap(),
-        constraints: SeqMap[String, expr.ValueExpr] = SeqMap(),
-    ): elem.PortLike = elem.PortLike(`is` =
-      elem.PortLike.Is.Port(elem.Port(
-        params = params.toPb,
-        constraints = constraints.toPb,
-        selfClass = selfClass match {
-          case "" => None
-          case selfClass => Some(LibraryPath(selfClass))
-        }
-      ))
-    )
-
-    def Bundle(
         selfClass: String,
         params: SeqMap[String, init.ValInit] = SeqMap(),
         ports: SeqMap[String, elem.PortLike] = SeqMap(),
         constraints: SeqMap[String, expr.ValueExpr] = SeqMap(),
     ): elem.PortLike = elem.PortLike(`is` =
-      elem.PortLike.Is.Bundle(elem.Bundle(
+      elem.PortLike.Is.Port(elem.Port(
         params = params.toPb,
         ports = ports.toPb,
         constraints = constraints.toPb,
         selfClass = selfClass match {
           case "" => None
-          case superclass => Some(LibraryPath(superclass))
+          case selfClass => Some(LibraryPath(selfClass))
         }
       ))
     )
@@ -306,10 +291,6 @@ object ElemBuilder {
             _.`is` match {
               case elem.PortLike.Is.Port(port) =>
                 port.getSelfClass.toFullString -> schema.Library.NS.Val(`type` = schema.Library.NS.Val.Type.Port(port))
-              case elem.PortLike.Is.Bundle(bundle) =>
-                bundle.getSelfClass.toFullString -> schema.Library.NS.Val(`type` =
-                  schema.Library.NS.Val.Type.Bundle(bundle)
-                )
               case port => throw new NotImplementedError(s"Unknown PortLike in library $port")
             }
           }.toMap

compiler/src/main/scala/edg/compiler/Compiler.scala

@@ -117,7 +117,7 @@ class AssignNamer() {
 }
 
 object Compiler {
-  final val kExpectedProtoVersion = 7
+  final val kExpectedProtoVersion = 8
 }
 
 /** Compiler for a particular design, with an associated library to elaborate references from.
@@ -289,7 +289,7 @@ class Compiler private (
 
     // Add sub-ports to the elaboration dependency graph, as appropriate
     toLinkPort match {
-      case toLinkPort: wir.Bundle =>
+      case toLinkPort: wir.Port =>
         for (portName <- toLinkPort.getPorts.keys) {
           elaboratePending.addNode(
             ElaborateRecord.Connect(
@@ -320,7 +320,7 @@ class Compiler private (
       // Returns the deepest applicable postfix, starting from a port
       def resolveRecursive(portPath: DesignPath, port: wir.PortLike, postfix: Seq[String]): Seq[String] = {
         port match {
-          case _: wir.Port | _: wir.Bundle | _: wir.PortLibrary => // don't recurse into these
+          case _: wir.Port | _: wir.PortLibrary => // don't recurse into these
             // note that libraries in arrays may not yet have been elaborated
             Seq()
           case port: wir.PortArray =>
@@ -416,12 +416,11 @@ class Compiler private (
         val portPb = library.getPort(libraryPath) match {
           case Errorable.Success(portPb) => portPb
           case Errorable.Error(err) =>
-            import edg.IrPort
             import edgir.elem.elem
             errors += CompilerError.LibraryError(path, libraryPath, err)
-            IrPort.Port(elem.Port())
+            elem.Port()
         }
-        val newPort = wir.PortLike.fromIrPort(portPb)
+        val newPort = new wir.Port(portPb)
         container.elaborate(path.lastString, newPort)
         newPort
       case port: wir.PortArray => port // no instantiation needed
@@ -434,9 +433,6 @@ class Compiler private (
       case port: wir.Port =>
         constProp.addAssignValue(path.asIndirect + IndirectStep.Name, TextValue(path.toString), containerPath, "name")
         processParamDeclarations(path, port)
-      case port: wir.Bundle =>
-        constProp.addAssignValue(path.asIndirect + IndirectStep.Name, TextValue(path.toString), containerPath, "name")
-        processParamDeclarations(path, port)
         for ((childPortName, childPort) <- port.getPorts) {
           elaboratePort(path + childPortName, containerPath, port, childPort)
         }
@@ -1135,7 +1131,7 @@ class Compiler private (
 
                 case connects => throw new IllegalArgumentException(s"invalid connections to array $connects")
               }
-            case _ => // non-array, eg Port or Bundle
+            case _ => // non-array, eg Port
               connectedConstraints.connectionsByLinkPort(portPostfix, false) match {
                 case PortConnections.ArrayConnect(constrName, constr) => constr.expr match {
                     case expr.ValueExpr.Expr.ConnectedArray(connected) =>
@@ -1196,7 +1192,7 @@ class Compiler private (
 
     // TODO refactor this out, ConnectedLink needs to be centralized
     def setConnectedLink(portPath: DesignPath, port: PortLike): Unit = (port: @unchecked) match {
-      case _: wir.Port | _: wir.Bundle =>
+      case _: wir.Port =>
         constProp.setConnectedLink(path, portPath)
       case port: wir.PortArray =>
         port.getPorts.foreach { case (subPortName, subPort) =>
@@ -1404,7 +1400,7 @@ class Compiler private (
       link.getModelPorts(portPostfix(1)) match {
         case _: wir.PortArray =>
           (portPostfix.init, (constrName, constr)) // drop the array index
-        case _ => // non-array like Port and Bundle
+        case _ => // non-array like Port
           (portPostfix, (constrName, constr))
       }
     }.groupBy(_._1).foreach { case (portPostfix, elts) => // actually resolve (delayed if array)
@@ -1420,7 +1416,7 @@ class Compiler private (
               ElaborateRecord.ElaboratePortArray(path ++ portPostfix)
             )
           )
-        case _ => // non-array like Port and Bundle
+        case _ => // non-array like Port
           val Seq((constrName, constr)) = constrNamesConstrs // can only be one element
           resolvePortConnectivity(path, portPostfix, Some(constrName, constr))
       }

compiler/src/main/scala/edg/compiler/DesignAssertionCheck.scala

@@ -33,9 +33,8 @@ class DesignAssertionCheck(compiler: Compiler)
     }
   }
 
-  override def mapPort(path: DesignPath, port: elem.Port): Unit = {}
+  override def mapPort(path: DesignPath, port: elem.Port, ports: SeqMap[String, Unit]): Unit = {}
   override def mapPortArray(path: DesignPath, port: elem.PortArray, ports: SeqMap[String, Unit]): Unit = {}
-  override def mapBundle(path: DesignPath, port: elem.Bundle, ports: SeqMap[String, Unit]): Unit = {}
   override def mapPortLibrary(path: DesignPath, port: ref.LibraryPath): Unit = {}
 
   override def mapBlock(

compiler/src/main/scala/edg/compiler/DesignMap.scala

@@ -16,15 +16,12 @@ trait DesignMap[PortType, BlockType, LinkType] {
 
   // These methods handle how nodes are processed must be overridden by the user where appropriate
   // (left default, they will exception out, which may be desired behavior on unexpected node types)
-  def mapPort(path: DesignPath, port: elem.Port): PortType = {
+  def mapPort(path: DesignPath, port: elem.Port, ports: SeqMap[String, PortType]): PortType = {
     throw new NotImplementedError(s"Undefined mapPort at $path")
   }
   def mapPortArray(path: DesignPath, port: elem.PortArray, ports: SeqMap[String, PortType]): PortType = {
     throw new NotImplementedError(s"Undefined mapPortArray at $path")
   }
-  def mapBundle(path: DesignPath, port: elem.Bundle, ports: SeqMap[String, PortType]): PortType = {
-    throw new NotImplementedError(s"Undefined mapBundle at $path")
-  }
   def mapPortLibrary(path: DesignPath, port: ref.LibraryPath): PortType = {
     throw new NotImplementedError(s"Undefined mapPortLibrary at $path")
   }
@@ -64,11 +61,11 @@ trait DesignMap[PortType, BlockType, LinkType] {
 
   // These methods provide default recursive processing functionality for child sub-tree elements,
   // and may be (but are not required to be) optionally overridden
-  def wrapBundle(path: DesignPath, port: elem.Bundle): PortType = {
+  def wrapPort(path: DesignPath, port: elem.Port): PortType = {
     val ports = port.ports.toSeqMap.map { case (name, elt) =>
       name -> wrapPortlike(path + name, elt)
     }
-    mapBundle(path, port, ports)
+    mapPort(path, port, ports)
   }
 
   def wrapPortArray(path: DesignPath, port: elem.PortArray): PortType = {
@@ -80,8 +77,7 @@ trait DesignMap[PortType, BlockType, LinkType] {
 
   def wrapPortlike(path: DesignPath, portLike: elem.PortLike): PortType = {
     portLike.is match {
-      case elem.PortLike.Is.Port(port) => mapPort(path, port)
-      case elem.PortLike.Is.Bundle(port) => wrapBundle(path, port)
+      case elem.PortLike.Is.Port(port) => wrapPort(path, port)
       case elem.PortLike.Is.Array(port) => wrapPortArray(path, port)
       case elem.PortLike.Is.LibElem(port) => mapPortLibrary(path, port)
       case block => throw new NotImplementedError(s"Unknown BlockLike type at $path: $block")
@@ -150,9 +146,8 @@ trait DesignBlockMap[BlockType] extends DesignMap[Unit, BlockType, Unit] {
 
   // These methods handle how nodes are processed must be overridden by the user where appropriate
   // (left default, they will exception out, which may be desired behavior on unexpected node types)
-  final override def mapPort(path: DesignPath, port: elem.Port): Unit = {}
+  final override def mapPort(path: DesignPath, port: elem.Port, ports: SeqMap[String, Unit]): Unit = {}
   final override def mapPortArray(path: DesignPath, port: elem.PortArray, ports: SeqMap[String, Unit]): Unit = {}
-  final override def mapBundle(path: DesignPath, port: elem.Bundle, ports: SeqMap[String, Unit]): Unit = {}
   final override def mapPortLibrary(path: DesignPath, port: ref.LibraryPath): Unit = {}
 
   final override def mapBlock(

compiler/src/main/scala/edg/compiler/DesignRefsValidate.scala

@@ -144,17 +144,13 @@ class DesignRefsValidate extends DesignMap[Unit, Unit, Unit] {
     }
   }
 
-  override def mapPort(path: DesignPath, port: elem.Port): Unit = {
+  override def mapPort(path: DesignPath, port: elem.Port, ports: SeqMap[String, Unit]): Unit = {
     port.params.asPairs.foreach { case (name, _) => paramDefs.add(path + name) }
     portDefs.add(path)
   }
   override def mapPortArray(path: DesignPath, port: elem.PortArray, ports: SeqMap[String, Unit]): Unit = {
     // do nothing
   }
-  override def mapBundle(path: DesignPath, port: elem.Bundle, ports: SeqMap[String, Unit]): Unit = {
-    port.params.asPairs.foreach { case (name, _) => paramDefs.add(path + name) }
-    portDefs.add(path)
-  }
   override def mapPortLibrary(path: DesignPath, port: ref.LibraryPath): Unit = {
     Seq(CompilerError.LibraryElement(path, port))
   }

compiler/src/main/scala/edg/compiler/DesignStructuralValidate.scala

@@ -12,8 +12,12 @@ import scala.collection.SeqMap
   *   - unelaborated library elements
   */
 class DesignStructuralValidate extends DesignMap[Seq[CompilerError], Seq[CompilerError], Seq[CompilerError]] {
-  override def mapPort(path: DesignPath, port: elem.Port): Seq[CompilerError] = {
-    Seq()
+  override def mapPort(
+      path: DesignPath,
+      port: elem.Port,
+      ports: SeqMap[String, Seq[CompilerError]]
+  ): Seq[CompilerError] = {
+    ports.values.flatten.toSeq
   }
   override def mapPortArray(
       path: DesignPath,
@@ -27,13 +31,6 @@ class DesignStructuralValidate extends DesignMap[Seq[CompilerError], Seq[Compile
     }
     undefinedError ++ ports.values.flatten.toSeq
   }
-  override def mapBundle(
-      path: DesignPath,
-      port: elem.Bundle,
-      ports: SeqMap[String, Seq[CompilerError]]
-  ): Seq[CompilerError] = {
-    ports.values.flatten.toSeq
-  }
   override def mapPortLibrary(path: DesignPath, port: ref.LibraryPath): Seq[CompilerError] = {
     Seq(CompilerError.LibraryElement(path, port))
   }

compiler/src/main/scala/edg/compiler/PythonInterface.scala

@@ -1,7 +1,6 @@
 package edg.compiler
 
 import edg.EdgirUtils.SimpleLibraryPath
-import edg.IrPort
 import edg.util.{Errorable, QueueStream, timeExec}
 import edg.wir.{DesignPath, IndirectDesignPath, Library}
 import edgir.elem.elem
@@ -393,9 +392,8 @@ class PythonInterfaceLibrary() extends Library {
     case (path, schema.Library.NS.Val.Type.HierarchyBlock(block)) => (path, block)
   }.toMap
 
-  override def allPorts: Map[ref.LibraryPath, IrPort] = elts.collect {
-    case (path, schema.Library.NS.Val.Type.Port(port)) => (path, IrPort.Port(port))
-    case (path, schema.Library.NS.Val.Type.Bundle(port)) => (path, IrPort.Bundle(port))
+  override def allPorts: Map[ref.LibraryPath, elem.Port] = elts.collect {
+    case (path, schema.Library.NS.Val.Type.Port(port)) => (path, port)
   }.toMap
 
   override def allLinks: Map[ref.LibraryPath, elem.Link] = elts.collect {
@@ -417,10 +415,9 @@ class PythonInterfaceLibrary() extends Library {
       case schema.Library.NS.Val.Type.Link(member) => member
     }
   }
-  override def getPort(path: ref.LibraryPath): Errorable[IrPort] = {
+  override def getPort(path: ref.LibraryPath): Errorable[elem.Port] = {
     getLibraryPartialMapped(path, "port") {
-      case schema.Library.NS.Val.Type.Port(member) => IrPort.Port(member)
-      case schema.Library.NS.Val.Type.Bundle(member) => IrPort.Bundle(member)
+      case schema.Library.NS.Val.Type.Port(member) => member
     }
   }
 

compiler/src/main/scala/edg/wir/BlockConnectivityAnalysis.scala

@@ -36,7 +36,6 @@ object BlockConnectivityAnalysis {
   def typeOfPortLike(portLike: elem.PortLike): ref.LibraryPath = portLike.is match {
     case elem.PortLike.Is.LibElem(lib) => lib
     case elem.PortLike.Is.Port(port) => port.getSelfClass
-    case elem.PortLike.Is.Bundle(port) => port.getSelfClass
     case elem.PortLike.Is.Array(port) => port.getSelfClass
     case other => throw new IllegalArgumentException(s"Unexpected PortLike ${other.getClass}")
   }

compiler/src/main/scala/edg/wir/Library.scala

@@ -1,7 +1,6 @@
 package edg.wir
 
 import edg.EdgirUtils.SimpleLibraryPath
-import edg.IrPort
 import edg.compiler.ExprValue
 import edg.util.Errorable
 import edg.wir.ProtoUtil.{
@@ -30,11 +29,11 @@ trait Library {
   // subclass relations
   def getBlock(path: ref.LibraryPath, ignoreRefinements: Boolean = false): Errorable[elem.HierarchyBlock]
   def getLink(path: ref.LibraryPath): Errorable[elem.Link]
-  def getPort(path: ref.LibraryPath): Errorable[IrPort]
+  def getPort(path: ref.LibraryPath): Errorable[elem.Port]
 
   // Returns all elements of the specified type and their path.
   // If the library has a mutable backing, this may change over time.
-  def allPorts: Map[ref.LibraryPath, IrPort]
+  def allPorts: Map[ref.LibraryPath, elem.Port]
   def allBlocks: Map[ref.LibraryPath, elem.HierarchyBlock]
   def allLinks: Map[ref.LibraryPath, elem.Link]
 
@@ -85,7 +84,6 @@ class EdgirLibrary(pb: schema.Library) extends Library {
     val libraryPath = ref.LibraryPath(target = Some(ref.LocalStep(step = ref.LocalStep.Step.Name(name))))
     member.`type` match {
       case schema.Library.NS.Val.Type.Port(_) => libraryPath -> member.`type`
-      case schema.Library.NS.Val.Type.Bundle(_) => libraryPath -> member.`type`
       case schema.Library.NS.Val.Type.HierarchyBlock(_) => libraryPath -> member.`type`
       case schema.Library.NS.Val.Type.Link(_) => libraryPath -> member.`type`
       case schema.Library.NS.Val.Type.Namespace(_) =>
@@ -98,9 +96,8 @@ class EdgirLibrary(pb: schema.Library) extends Library {
     case (path, schema.Library.NS.Val.Type.HierarchyBlock(block)) => (path, block)
   }
 
-  override def allPorts: Map[ref.LibraryPath, IrPort] = elts.collect {
-    case (path, schema.Library.NS.Val.Type.Port(port)) => (path, IrPort.Port(port))
-    case (path, schema.Library.NS.Val.Type.Bundle(port)) => (path, IrPort.Bundle(port))
+  override def allPorts: Map[ref.LibraryPath, elem.Port] = elts.collect {
+    case (path, schema.Library.NS.Val.Type.Port(port)) => (path, port)
   }
 
   override def allLinks: Map[ref.LibraryPath, elem.Link] = elts.collect {
@@ -121,9 +118,8 @@ class EdgirLibrary(pb: schema.Library) extends Library {
     case None => Errorable.Error(s"Library does not contain $path")
   }
 
-  override def getPort(path: ref.LibraryPath): Errorable[IrPort] = elts.get(path) match {
-    case Some(schema.Library.NS.Val.Type.Port(member)) => Errorable.Success(IrPort.Port(member))
-    case Some(schema.Library.NS.Val.Type.Bundle(member)) => Errorable.Success(IrPort.Bundle(member))
+  override def getPort(path: ref.LibraryPath): Errorable[elem.Port] = elts.get(path) match {
+    case Some(schema.Library.NS.Val.Type.Port(member)) => Errorable.Success(member)
     case Some(member) => Errorable.Error(s"Library element at $path not a port-like, got ${member.getClass}")
     case None => Errorable.Error(s"Library does not contain $path")
   }