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Pr187 - Verilator warnings #188

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MM871 wants to merge 27 commits intomainfrom
pr187
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Pr187 - Verilator warnings #188
MM871 wants to merge 27 commits intomainfrom
pr187

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@MM871 MM871 commented Feb 22, 2026

all 5 changes seem to be present in this one

@TheDeepestSpace TheDeepestSpace linked an issue Feb 22, 2026 that may be closed by this pull request
zba uut(.reg1(reg1)
, .reg2(reg2)
, .inst(inst)
, .funct3(3'b000) //these were missing
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Suggested change
, .funct3(3'b000) //these were missing
, .funct3(3'b000)

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github-actions bot commented Mar 15, 2026

🔧 DE1-SoC Synthesis Report Summary Diff

📊 Fitter Summary (.fit.summary)

@@ -1,4 +1,4 @@
-Fitter Status : Successful - Sun Mar 15 05:34:01 2026
+Fitter Status : Successful - Thu Mar 19 14:52:55 2026
 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
 Revision Name : utoss-risc-v
 Top-level Entity Name : top

⏱️ Timing Analysis Summary (.sta.summary)

No changes detected


Comparing synthesis results from main branch vs. this PR

, .memory_address ( memory__address )
, .memory_data ( mem_load_result )
, .write_enable ( memory__write_enable )
, .write_enable ( memory__write_enable[0] )
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i think it would be better to expand write_enable signal in Logger to support 4 bits, just so that we are not missing out on this info in the debug logs.

else if (opcode == RType) next_state = EXECUTER;

else if (opcode == IType_logic) next_state = EXECUTEI;
else if (opcode == IType_logic) next_state = EXECUTEI; // "7'b0010011" was reverted back to "IType_logic"
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Suggested change
else if (opcode == IType_logic) next_state = EXECUTEI; // "7'b0010011" was reverted back to "IType_logic"
else if (opcode == IType_logic) next_state = EXECUTEI;

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Address Linter issues from TTO repo

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