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…STAR, WIDTHTRUNC, port widths
…LENAME, IMPORTSTAR, WIDTHTRUNC, and a write-enable line from utoss_riscv.sv
| zba uut(.reg1(reg1) | ||
| , .reg2(reg2) | ||
| , .inst(inst) | ||
| , .funct3(3'b000) //these were missing |
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| , .funct3(3'b000) //these were missing | |
| , .funct3(3'b000) |
…conflict resolution issue
…eferencing old filenames
🔧 DE1-SoC Synthesis Report Summary Diff📊 Fitter Summary (.fit.summary)@@ -1,4 +1,4 @@
-Fitter Status : Successful - Sun Mar 15 05:34:01 2026
+Fitter Status : Successful - Thu Mar 19 14:52:55 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : utoss-risc-v
Top-level Entity Name : top⏱️ Timing Analysis Summary (.sta.summary)No changes detected Comparing synthesis results from main branch vs. this PR |
| , .memory_address ( memory__address ) | ||
| , .memory_data ( mem_load_result ) | ||
| , .write_enable ( memory__write_enable ) | ||
| , .write_enable ( memory__write_enable[0] ) |
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i think it would be better to expand write_enable signal in Logger to support 4 bits, just so that we are not missing out on this info in the debug logs.
| else if (opcode == RType) next_state = EXECUTER; | ||
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| else if (opcode == IType_logic) next_state = EXECUTEI; | ||
| else if (opcode == IType_logic) next_state = EXECUTEI; // "7'b0010011" was reverted back to "IType_logic" |
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| else if (opcode == IType_logic) next_state = EXECUTEI; // "7'b0010011" was reverted back to "IType_logic" | |
| else if (opcode == IType_logic) next_state = EXECUTEI; |
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all 5 changes seem to be present in this one