Pr187 - Verilator warnings

Makefile

@@ -27,8 +27,7 @@ UTOSS_RISCV_VERILATOR_DEFINES := $(if $(findstring B,$(UTOSS_RISCV_CONFIG)),-DUT
 # Verilator flags
 # ===========================
 
-VERILATOR_FLAGS := -Wall --binary --trace --timing -sv -cc \
-	-O3 -Wno-fatal $(UTOSS_RISCV_VERILATOR_DEFINES)
+VERILATOR_FLAGS := -Wall --binary --trace --timing -sv -cc -O3 $(UTOSS_RISCV_VERILATOR_DEFINES)
 
 # Testbench-only defines
 TB_DEFINES := -DTESTBENCH

envs/de1-soc/quartus/utoss-risc-v.qsf

@@ -313,13 +313,13 @@ set_location_assignment PIN_F13 -to VGA_R[7]
 set_location_assignment PIN_C10 -to VGA_SYNC_N
 set_location_assignment PIN_D11 -to VGA_VS
 
-set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/packages/pkg_control_fsm.sv
+set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/packages/pkg_control_fsm.svh
 set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/utils.svh
 set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/types.svh
 set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/params.svh
 set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/ALU_ALUdecoder/ALUdecoder.sv
+set_global_assignment -name VERILOG_FILE ../../../src/Instruction_Decode/registerFile.v
 set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/ALU_ALUdecoder/ALU.sv
-set_global_assignment -name VERILOG_FILE ../../../src/Instruction_Decode/RegisterFile.v
 set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/Instruction_Decode/MemoryLoader.sv
 set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/Instruction_Decode/Instruction_Decode.sv
 set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/utoss_riscv.sv
@@ -328,4 +328,4 @@ set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/ControlFSM.sv
 set_global_assignment -name SYSTEMVERILOG_FILE ../top.sv
 set_global_assignment -name SYSTEMVERILOG_FILE ../memory_map.sv
 set_global_assignment -name SDC_FILE "utoss-risc-v.sdc"
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

envs/de1-soc/top_tb.sv

@@ -1,4 +1,4 @@
-`timescale 1ns/1ps
+`include "src/timescale.svh"
 
 module top_tb;
 

envs/simulation/MA.sv

@@ -1,3 +1,6 @@
+`include "src/timescale.svh"
+
+
 module MA #( parameter SIZE = 1024 )
   ( input  wire         clk
   , input  addr_t       address
@@ -20,13 +23,25 @@ module MA #( parameter SIZE = 1024 )
   end
 `endif
 
+  localparam int unsigned SIZE_W = $clog2(SIZE);
+
+  if (SIZE_W >= `PROCESSOR_BITNESS) begin: l_check_size
+    initial begin
+      $fatal(1, "memory is too large to be addressed by a %d-bit address", `PROCESSOR_BITNESS);
+    end
+  end
+
+  wire unused = &{address[`PROCESSOR_BITNESS -1:SIZE_W], address[1:0]};
+
   always @(posedge clk) begin
-    read_data <= M[address[31:2]]; // 2 LSBs used for byte addressing
+    read_data <= M[address[SIZE_W +1:2]]; // 2 LSBs used for byte addressing
+                                  // changed width from 32:2 to 9:0 to match "logic [1023:0] M;"
 
-    if (write_enable[0]) M[address[31:2]][7:0]   <= write_data[7:0];
-    if (write_enable[1]) M[address[31:2]][15:8]  <= write_data[15:8];
-    if (write_enable[2]) M[address[31:2]][23:16] <= write_data[23:16];
-    if (write_enable[3]) M[address[31:2]][31:24] <= write_data[31:24];
+    if (write_enable[0]) M[address[SIZE_W + 1:2]][7:0]   <= write_data[7:0];
+    if (write_enable[1]) M[address[SIZE_W + 1:2]][15:8]  <= write_data[15:8];
+    if (write_enable[2]) M[address[SIZE_W + 1:2]][23:16] <= write_data[23:16];
+    if (write_enable[3]) M[address[SIZE_W + 1:2]][31:24] <= write_data[31:24];
   end
 
+
 endmodule

envs/simulation/top.sv

@@ -1,4 +1,6 @@
 `include "src/types.svh"
+`timescale 1ns/1ps
+
 
 module top
   #( parameter MEM_SIZE = 1024 )

riscof/dut.sv

@@ -1,4 +1,4 @@
-`timescale 1ns/1ps
+`include "src/timescale.svh"
 
 `include "test/utils.svh"
 
@@ -19,9 +19,9 @@ module dut;
   end
 
   initial begin
-    reset <= `TRUE;
+    reset = `TRUE;
     @(posedge clk); #1;
-    reset <= `FALSE;
+    reset = `FALSE;
 
     fork
       watch_tohost();
@@ -32,16 +32,18 @@ module dut;
   end
 
   task watch_tohost();
+    /* verilator lint_off UNUSEDSIGNAL */
     integer tohost;
     reg [31:0] tohost_data;
+    /* verilator lint_on UNUSEDSIGNAL */
 
     $display("%m: waiting for tohost...");
     if ($value$plusargs("tohost=%h", tohost)) begin
       $display("%m: watching tohost at address <%0d>", tohost);
 
       while (tohost_data === 0 || tohost_data === 32'bx) begin
         @(posedge clk);
-        tohost_data = top.memory.M[tohost[31:2]];
+        tohost_data = top.memory.M[19'(tohost[31:2])];
       end
 
       $display("%m: memory[tohost] written <%0d> at time %t", tohost_data, $time);
@@ -53,15 +55,22 @@ module dut;
 
   task watch_timeout();
     $display("%m: waiting for timeout...");
+
+    /* verilator lint_off UNUSEDSIGNAL */
     repeat (100000) @(posedge clk);
+    /* verilator lint_on UNUSEDSIGNAL */
+
     $display("%m: timeout reached");
     void'(extract_signature());
   endtask
 
   function bit extract_signature();
+    /* verilator lint_off UNUSEDSIGNAL */
     integer begin_signature, end_signature;
     string sig_filename;
-    integer sig_file, i, i_fixed;
+    integer sig_file, i;
+    //integer i_fixed;
+    /* verilator lint_on UNUSEDSIGNAL */
 
     if (!$value$plusargs("begin_signature=%h", begin_signature)) begin
       $display("%m: begin_signature not specified.");
@@ -81,7 +90,7 @@ module dut;
     sig_file = $fopen(sig_filename, "w");
     if (sig_file != 0) begin
       for (i = begin_signature; i < end_signature; i = i + 4) begin
-        $fwrite(sig_file, "%08x\n", top.memory.M[i[31:2]]);
+        $fwrite(sig_file, "%08x\n", top.memory.M[19'(i[31:2])]);
       end
       $fclose(sig_file);
       $display("%m: signature written to %s", sig_filename);

src/ALU_ALUdecoder/ALU.sv

@@ -1,4 +1,6 @@
 `include "src/types.svh"
+`include "src/timescale.svh"
+
 module ALU
 (
   input logic [31:0] a
@@ -25,4 +27,4 @@ always_comb
 
 assign zeroE = (out == 0);
 
-endmodule
+endmodule

src/ALU_ALUdecoder/ALUdecoder.sv

@@ -1,4 +1,6 @@
 `include "src/types.svh"
+`include "src/timescale.svh"
+
 
 module ALUdecoder (
       input  [2:0] funct3
@@ -76,4 +78,4 @@ module ALUdecoder (
     endcase
   end
 
-endmodule
+endmodule

src/ControlFSM.sv

@@ -1,11 +1,15 @@
 //created by Joonseo Park, for University of Toronto Open Source Society
 //A Moore Type Finite State Machine for the RV32I Microprocessor Control Unit
 
+`include "src/timescale.svh"
 `include "src/types.svh"
 `include "src/params.svh"
 `include "src/packages/pkg_control_fsm.svh"
 
+
+/* verilator lint_off IMPORTSTAR */
 import pkg_control_fsm::*;
+/* verilator lint_on IMPORTSTAR */
 
 module ControlFSM
   ( input opcode_t opcode
@@ -42,9 +46,7 @@ module ControlFSM
       DECODE: begin
 
         if (opcode == JType) next_state = UNCONDJUMP;
-
         else if (opcode == RType) next_state = EXECUTER;
-
         else if (opcode == IType_logic) next_state = EXECUTEI;
 
         else if (opcode == IType_load || opcode == SType) next_state = MEMADR;
@@ -118,6 +120,7 @@ module ControlFSM
   end
 
   //output logic
+
   always @(*) begin
     Branch = 1'b0;
     pc_src = PC_SRC__INCREMENT;
@@ -233,6 +236,7 @@ module ControlFSM
             end
             else pc_src = PC_SRC__INCREMENT;
           end
+          default:;
         endcase
       end
 
@@ -244,14 +248,14 @@ module ControlFSM
         Branch = 1'b1;
         case (funct3)
           3'b100, 3'b110: begin // BLT, BLTU: branch if rs1 < rs2
-            if (alu_result) begin // Direct SLT/SLTU result
+            if (alu_result[0]) begin // Direct SLT/SLTU result
               pc_src = PC_SRC__JUMP;
               PCUpdate = 1'b1;
             end
             else pc_src = PC_SRC__INCREMENT;
           end
           3'b101, 3'b111: begin // BGE, BGEU: branch if rs1 >= rs2 (invert SLT/SLTU)
-            if (!alu_result) begin // Invert SLT/SLTU result for >= comparison
+            if (!alu_result[0]) begin // Invert SLT/SLTU result for >= comparison
               pc_src = PC_SRC__JUMP;
               PCUpdate = 1'b1;
             end
@@ -263,7 +267,6 @@ module ControlFSM
       end
 
       ALUWB: begin
-
         ResultSrc = RESULT_SRC__ALU_OUT;
         RegWrite = 1'b1;
 
@@ -285,7 +288,6 @@ module ControlFSM
       end
 
       MEMWB: begin
-
         ResultSrc = RESULT_SRC__DATA;
         RegWrite = 1'b1;
 
@@ -313,4 +315,7 @@ module ControlFSM
     end
 
   end
+
+  wire unused = &{alu_result[31:1]};
+
 endmodule

src/Instruction_Decode/Instruction_Decode.sv

@@ -1,4 +1,5 @@
 `include "src/params.svh"
+`include "src/timescale.svh"
 `include "src/types.svh"
 
 module Instruction_Decode
@@ -16,15 +17,20 @@ module Instruction_Decode
   alu_op_t alu_op;
   // reg [2:0] funct3;
   // reg [6:0] funct7;
+
+  /* verilator lint_off UNUSEDSIGNAL */
   wire [3:0] state;
+  /* verilator lint_on UNUSEDSIGNAL */
+
 
   assign opcode = instr[6:0];
 
   //combinational logic for extracting funct3 and funct7[5] for ALU Decoder input
 
+  /* verilator lint_off UNUSEDSIGNAL */
   reg [2:0] default_funct3;
   reg [6:0] default_funct7;
-
+  /* verilator lint_on UNUSEDSIGNAL */
   always @(*) begin
 
     funct3 = 3'b000;
@@ -44,7 +50,7 @@ module Instruction_Decode
       funct3 = instr[14:12];
 
     end
-
+    default:;
     endcase
   end
 
@@ -61,7 +67,6 @@ module Instruction_Decode
       UType_lui:   alu_op = ALU_OP__ADD; // used to add 0 to imm ext
       FENCE:     alu_op = ALU_OP__UNSET;
       default:    alu_op = ALU_OP__UNSET;
-
     endcase
   end
 
@@ -119,8 +124,8 @@ module Instruction_Decode
       SType       : imm_ext = {{20{instr[31]}}, instr[31:25], instr[11:7]};
       BType       : imm_ext = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0};
       JType       : imm_ext = {{12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0};
-      UType_auipc  : imm_ext = {instr[31:12], 12'b0};
-      UType_lui  : imm_ext = {instr[31:12], 12'b0};
+      UType_auipc  : imm_ext = {instr[31:12], 12'h000};
+      UType_lui  : imm_ext = {instr[31:12], 12'h000};
       default:     imm_ext = 32'b0;
     endcase
   end
@@ -133,11 +138,10 @@ module Instruction_Decode
     , .alu_op(alu_op)
     , .alu_control(ALUControl)
     );
-
 `ifdef UTOSS_RISCV_ENABLE_B_EXT
-
+/* verilator lint_off UNUSEDSIGNAL */
   ext__b__types::b_alu_control_t b_alu_control;
-
+/* verilator lint_on UNUSEDSIGNAL */
   ext__b__decoder u_ext__b__decoder
     ( .funct3        ( funct3        )
     , .funct7        ( funct7        )

src/Instruction_Decode/MemoryLoader.sv

@@ -2,7 +2,11 @@
 
 module MemoryLoader
 ( input  data_t memory_data
+
+/* verilator lint_off UNUSEDSIGNAL */
 , input  addr_t memory_address
+/* verilator lint_on UNUSEDSIGNAL */
+
 , input  logic [2:0]  funct3
 , input  logic [31:0] dataB
 , output data_t mem_load_result
@@ -13,14 +17,18 @@ module MemoryLoader
     logic [1:0] byteindex;
     assign byteindex = memory_address[1:0];
 
+    /* verilator lint_off WIDTHTRUNC */     //this entire block was commented out - reverted
     typedef enum logic [1:0]
     { BYTE = 2'b00
     , HALF = 2'b01
     , WORD = 2'b10
     } transfersize_t;
+    /* verilator lint_on WIDTHTRUNC */
 
     logic signed_mode;
-    assign signed_mode = ~funct3[2];
+    /* verilator lint_off WIDTHTRUNC */
+    assign signed_mode = ~funct3[2]; // reverted from "(funct3[2] == 1'b0);"
+    /* verilator lint_on WIDTHTRUNC */
 
     always @(*) // cannot use always_comb yet: https://github.com/steveicarus/iverilog/issues/734
         case (funct3[1:0])
@@ -85,4 +93,5 @@ module MemoryLoader
                 MemWriteByteAddress = 4'bxxxx;
             end
         endcase
-endmodule
+endmodule
+