LLVM integrated assembler - nanoMIPS port#1
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farazs-github wants to merge 123 commits intonanomips-llvm13-submissionfrom
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LLVM integrated assembler - nanoMIPS port#1farazs-github wants to merge 123 commits intonanomips-llvm13-submissionfrom
farazs-github wants to merge 123 commits intonanomips-llvm13-submissionfrom
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Includes P.SHIFT, P.U12, P.INS, P.EXT
This isn't a full fix on its own though since RA is not actually flagged as non-allocable, and there's nothing that denotes 'clobbered by the calller's call instruction itself'
This was previously assuming both to have an implicit src operand. As per ISA, the source operand for ADDIUPC is implicit, while that for ADDIU[GP] is explicit.
Use PC-relative (ADDIUPC) instructions till we can resolve generating correct GP-relative instructions with %gp_rel
Signed-offset loads & stores don't have valid relocations and neither do any of the 16-bit loads & stores.
(accidentally commented in 9216bd1)
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