LLVM integrated assembler - nanoMIPS port

clang/lib/Driver/ToolChains/Clang.cpp

@@ -1990,9 +1990,6 @@ void Clang::AddMIPSTargetArgs(const ArgList &Args,
 
   // Enable interprocedural register allocation by default on NanoMips
   if (Triple.isNanoMips()) {
-    CmdArgs.push_back("-mllvm");
-    CmdArgs.push_back("-enable-ipra");
-
     // Change inlining thresholds.
     if (Arg *A = Args.getLastArg(options::OPT_O_Group)) {
       if (A->getOption().matches(options::OPT_O)) {

llvm/include/llvm/BinaryFormat/ELF.h

@@ -318,6 +318,7 @@ enum {
   EM_RISCV = 243,         // RISC-V
   EM_LANAI = 244,         // Lanai 32-bit processor
   EM_BPF = 247,           // Linux kernel bpf virtual machine
+  EM_NANOMIPS = 249,	  // MIPS Tech nanoMIPS architecture
   EM_VE = 251,            // NEC SX-Aurora VE
   EM_CSKY = 252,          // C-SKY 32-bit processor
 };
@@ -593,6 +594,38 @@ enum {
   ODK_PAGESIZE = 11   // Page size information
 };
 
+// ELF Relocation types for Mips
+enum {
+#include "ELFRelocs/NanoMips.def"
+};
+
+// NanoMips specific e_flags
+enum : unsigned {
+  // File may be relaxed by the linker.
+  EF_NANOMIPS_LINKRELAX = 0x00000001,
+  // File contains position independent code.
+  EF_NANOMIPS_PIC = 0x00000002,
+  // Indicates code compiled for a 64-bit machine in 32-bit mode
+  // (regs are 32-bits wide).
+  EF_NANOMIPS_32BITMODE = 0x00000004,
+  // Indicate that all data access in this object is GP-relative
+  EF_NANOMIPS_PID = 0x00000008,
+  // Indicate that this object does not use absolute addressing.
+  EF_NANOMIPS_PCREL = 0x00000010,
+  // Four bit nanoMIPS architecture field.
+  EF_NANOMIPS_ARCH = 0xf0000000,
+  // -march=32r6 code.
+  E_NANOMIPS_ARCH_32R6 = 0x00000000,
+  // -march=64r6 code.
+  E_NANOMIPS_ARCH_64R6 = 0x10000000,
+  // The ABI of the file.
+  EF_NANOMIPS_ABI = 0x0000f000,
+  // nanoMIPS ABI in 32 bit mode.
+  E_NANOMIPS_ABI_P32 = 0x00001000,
+  // nanoMIPS ABI in 64 bit mode.
+  E_NANOMIPS_ABI_P64 = 0x00002000
+};
+
 // Hexagon-specific e_flags
 enum {
   // Object processor version flags, bits[11:0]

llvm/include/llvm/BinaryFormat/ELFRelocs/NanoMips.def

@@ -0,0 +1,81 @@
+#ifndef ELF_RELOC
+#error "ELF_RELOC must be defined"
+#endif
+
+ELF_RELOC(R_NANOMIPS_NONE, 0)
+ELF_RELOC(R_NANOMIPS_32, 1)
+ELF_RELOC(R_NANOMIPS_64, 2)
+ELF_RELOC(R_NANOMIPS_NEG, 3)
+ELF_RELOC(R_NANOMIPS_ASHIFTR_1, 4)
+ELF_RELOC(R_NANOMIPS_UNSIGNED_8, 5)
+ELF_RELOC(R_NANOMIPS_SIGNED_8, 6)
+ELF_RELOC(R_NANOMIPS_UNSIGNED_16, 7)
+ELF_RELOC(R_NANOMIPS_SIGNED_16, 8)
+ELF_RELOC(R_NANOMIPS_RELATIVE, 9)
+ELF_RELOC(R_NANOMIPS_GLOBAL, 10)
+ELF_RELOC(R_NANOMIPS_JUMP_SLOT, 11)
+ELF_RELOC(R_NANOMIPS_IRELATIVE, 12)
+ELF_RELOC(R_NANOMIPS_PC25_S1, 13)
+ELF_RELOC(R_NANOMIPS_PC21_S1, 14)
+ELF_RELOC(R_NANOMIPS_PC14_S1, 15)
+ELF_RELOC(R_NANOMIPS_PC11_S1, 16)
+ELF_RELOC(R_NANOMIPS_PC10_S1, 17)
+ELF_RELOC(R_NANOMIPS_PC7_S1, 18)
+ELF_RELOC(R_NANOMIPS_PC4_S1, 19)
+ELF_RELOC(R_NANOMIPS_GPREL19_S2, 20)
+ELF_RELOC(R_NANOMIPS_GPREL18_S3, 21)
+ELF_RELOC(R_NANOMIPS_GPREL18, 22)
+ELF_RELOC(R_NANOMIPS_GPREL17_S1, 23)
+ELF_RELOC(R_NANOMIPS_GPREL16_S2, 24)
+ELF_RELOC(R_NANOMIPS_GPREL7_S2, 25)
+ELF_RELOC(R_NANOMIPS_GPREL_HI20, 26)
+ELF_RELOC(R_NANOMIPS_PCHI20, 27)
+ELF_RELOC(R_NANOMIPS_HI20, 28)
+ELF_RELOC(R_NANOMIPS_LO12, 29)
+ELF_RELOC(R_NANOMIPS_GPREL_I32, 30)
+ELF_RELOC(R_NANOMIPS_PC_I32, 31)
+ELF_RELOC(R_NANOMIPS_I32, 32)
+ELF_RELOC(R_NANOMIPS_GOT_DISP, 33)
+ELF_RELOC(R_NANOMIPS_GOTPC_I32, 34)
+ELF_RELOC(R_NANOMIPS_GOTPC_HI20, 35)
+ELF_RELOC(R_NANOMIPS_GOT_LO12, 36)
+ELF_RELOC(R_NANOMIPS_GOT_CALL, 37)
+ELF_RELOC(R_NANOMIPS_GOT_PAGE, 38)
+ELF_RELOC(R_NANOMIPS_GOT_OFST, 39)
+ELF_RELOC(R_NANOMIPS_LO4_S2, 40)
+ELF_RELOC(R_NANOMIPS_RESERVED1, 41)
+ELF_RELOC(R_NANOMIPS_GPREL_LO12, 42)
+ELF_RELOC(R_NANOMIPS_SCN_DISP, 43)
+ELF_RELOC(R_NANOMIPS_COPY, 44)
+ELF_RELOC(R_NANOMIPS_ALIGN, 64)
+ELF_RELOC(R_NANOMIPS_FILL, 65)
+ELF_RELOC(R_NANOMIPS_MAX, 66)
+ELF_RELOC(R_NANOMIPS_INSN32, 67)
+ELF_RELOC(R_NANOMIPS_FIXED, 68)
+ELF_RELOC(R_NANOMIPS_NORELAX, 69)
+ELF_RELOC(R_NANOMIPS_RELAX, 70)
+ELF_RELOC(R_NANOMIPS_SAVERESTORE, 71)
+ELF_RELOC(R_NANOMIPS_INSN16, 72)
+ELF_RELOC(R_NANOMIPS_JALR32, 73)
+ELF_RELOC(R_NANOMIPS_JALR16, 74)
+ELF_RELOC(R_NANOMIPS_JUMPTABLE_LOAD, 75)
+ELF_RELOC(R_NANOMIPS_FRAME_REG, 76)
+ELF_RELOC(R_NANOMIPS_TLS_DTPMOD, 80)
+ELF_RELOC(R_NANOMIPS_TLS_DTPREL, 81)
+ELF_RELOC(R_NANOMIPS_TLS_TPREL, 82)
+ELF_RELOC(R_NANOMIPS_TLS_GD, 83)
+ELF_RELOC(R_NANOMIPS_TLS_GD_I32, 84)
+ELF_RELOC(R_NANOMIPS_TLS_LD, 85)
+ELF_RELOC(R_NANOMIPS_TLS_LD_I32, 86)
+ELF_RELOC(R_NANOMIPS_TLS_DTPREL12, 87)
+ELF_RELOC(R_NANOMIPS_TLS_DTPREL16, 88)
+ELF_RELOC(R_NANOMIPS_TLS_DTPREL_I32, 89)
+ELF_RELOC(R_NANOMIPS_TLS_GOTTPREL, 90)
+ELF_RELOC(R_NANOMIPS_TLS_GOTTPREL_PC_I32, 91)
+ELF_RELOC(R_NANOMIPS_TLS_TPREL12, 92)
+ELF_RELOC(R_NANOMIPS_TLS_TPREL16, 93)
+ELF_RELOC(R_NANOMIPS_TLS_TPREL_I32, 94)
+ELF_RELOC(R_NANOMIPS_PC32, 248)
+ELF_RELOC(R_NANOMIPS_EH, 249)
+ELF_RELOC(R_NANOMIPS_GNU_VTINHERIT, 253)
+ELF_RELOC(R_NANOMIPS_GNU_VTENTRY, 254)

llvm/include/llvm/CodeGen/TargetRegisterInfo.h

@@ -565,6 +565,13 @@ class TargetRegisterInfo : public MCRegisterInfo {
   virtual bool isCalleeSavedPhysReg(MCRegister PhysReg,
                                     const MachineFunction &MF) const;
 
+  // Return true if the register is needed for returning from the
+  // function and so must be preserved in the callee even if preserved
+  // by the caller
+  virtual bool isNeededForReturn(MCRegister PhysReg, const MachineFunction &MF) const {
+    return false;
+  }
+
   /// Prior to adding the live-out mask to a stackmap or patchpoint
   /// instruction, provide the target the opportunity to adjust it (mainly to
   /// remove pseudo-registers that should be ignored).

llvm/include/llvm/module.modulemap

@@ -72,6 +72,7 @@ module LLVM_BinaryFormat {
     textual header "BinaryFormat/ELFRelocs/Lanai.def"
     textual header "BinaryFormat/ELFRelocs/M68k.def"
     textual header "BinaryFormat/ELFRelocs/Mips.def"
+    textual header "BinaryFormat/ELFRelocs/NanoMips.def"
     textual header "BinaryFormat/ELFRelocs/MSP430.def"
     textual header "BinaryFormat/ELFRelocs/PowerPC64.def"
     textual header "BinaryFormat/ELFRelocs/PowerPC.def"

llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp

@@ -87,10 +87,9 @@ void TargetFrameLowering::determineCalleeSaves(MachineFunction &MF,
 
   // When interprocedural register allocation is enabled caller saved registers
   // are preferred over callee saved registers.
-  if (MF.getTarget().Options.EnableIPRA &&
-      isSafeForNoCSROpt(MF.getFunction()) &&
-      isProfitableForNoCSROpt(MF.getFunction()))
-    return;
+  bool NoCSR = (MF.getTarget().Options.EnableIPRA &&
+                isSafeForNoCSROpt(MF.getFunction()) &&
+                isProfitableForNoCSROpt(MF.getFunction()));
 
   // Get the callee saved register list...
   const MCPhysReg *CSRegs = MF.getRegInfo().getCalleeSavedRegs();
@@ -119,10 +118,12 @@ void TargetFrameLowering::determineCalleeSaves(MachineFunction &MF,
   // Functions which call __builtin_unwind_init get all their registers saved.
   bool CallsUnwindInit = MF.callsUnwindInit();
   const MachineRegisterInfo &MRI = MF.getRegInfo();
+  const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
   for (unsigned i = 0; CSRegs[i]; ++i) {
     unsigned Reg = CSRegs[i];
     if (CallsUnwindInit || MRI.isPhysRegModified(Reg))
-      SavedRegs.set(Reg);
+      if (!NoCSR || !MRI.isAllocatable(Reg) || RI->isNeededForReturn(Reg, MF))
+        SavedRegs.set(Reg);
   }
 }
 

llvm/lib/MC/MCAsmStreamer.cpp

@@ -2166,7 +2166,7 @@ void MCAsmStreamer::AddEncodingComment(const MCInst &Inst,
     for (unsigned j = 0; j != Info.TargetSize; ++j) {
       unsigned Index = F.getOffset() * 8 + Info.TargetOffset + j;
       assert(Index < Code.size() * 8 && "Invalid offset in fixup!");
-      FixupMap[Index] = 1 + i;
+      FixupMap[(Index + 16) % (Code.size() * 8)] = 1 + i;
     }
   }
 

llvm/lib/Object/ELF.cpp

@@ -51,8 +51,15 @@ StringRef llvm::object::getELFRelocationTypeName(uint32_t Machine,
       break;
     }
     break;
+   case ELF::EM_NANOMIPS:
+     switch (Type) {
+#include "llvm/BinaryFormat/ELFRelocs/NanoMips.def"
+     default:
+       break;
+     }
+     break;
   case ELF::EM_AARCH64:
-    switch (Type) {
+      switch (Type) {
 #include "llvm/BinaryFormat/ELFRelocs/AArch64.def"
     default:
       break;
@@ -182,6 +189,7 @@ uint32_t llvm::object::getELFRelativeRelocationType(uint32_t Machine) {
   case ELF::EM_IAMCU:
     return ELF::R_386_RELATIVE;
   case ELF::EM_MIPS:
+  case ELF::EM_NANOMIPS:
     break;
   case ELF::EM_AARCH64:
     return ELF::R_AARCH64_RELATIVE;

llvm/lib/ObjectYAML/ELFYAML.cpp

@@ -787,6 +787,9 @@ void ScalarEnumerationTraits<ELFYAML::ELF_REL>::enumeration(
   case ELF::EM_MIPS:
 #include "llvm/BinaryFormat/ELFRelocs/Mips.def"
     break;
+  case ELF::EM_NANOMIPS:
+#include "llvm/BinaryFormat/ELFRelocs/NanoMips.def"
+    break;
   case ELF::EM_HEXAGON:
 #include "llvm/BinaryFormat/ELFRelocs/Hexagon.def"
     break;