[RISCV] Add support for R_RISCV_QC_ACCESS_16 and R_RISCV_QC_ACCESS_32

lib/Target/RISCV/RISCVRelocationInfo.cpp

@@ -738,6 +738,26 @@ RISCVRelocationMap RISCVRelocs = {
       /*.VerifyAlignment = */ true,
       /*.Signed = */ true,
       /*.Size = */ 48}},
+    {eld::ELF::riscv::internal::R_RISCV_QC_ACCESS_16,
+     {/*.Name = */ "R_RISCV_QC_ACCESS_16",
+      /*.Type = */ eld::ELF::riscv::internal::R_RISCV_QC_ACCESS_16,
+      /*EncodingType = */ EncTy_None,
+      /*.Alignment = */ 0,
+      /*.shift = */ 0,
+      /*.VerifyRange = */ false,
+      /*.VerifyAlignment = */ false,
+      /*.Signed = */ false,
+      /*.Size = */ 16}},
+    {eld::ELF::riscv::internal::R_RISCV_QC_ACCESS_32,
+     {/*.Name = */ "R_RISCV_QC_ACCESS_32",
+      /*.Type = */ eld::ELF::riscv::internal::R_RISCV_QC_ACCESS_32,
+      /*EncodingType = */ EncTy_None,
+      /*.Alignment = */ 0,
+      /*.shift = */ 0,
+      /*.VerifyRange = */ false,
+      /*.VerifyAlignment = */ false,
+      /*.Signed = */ false,
+      /*.Size = */ 32}},
 };
 
 } // namespace

lib/Target/RISCV/RISCVRelocationInternal.h

@@ -66,11 +66,11 @@ enum : uint32_t {
     added to the nonstandard ID to get the internal ID.
   */
   FirstInternalRelocation = 320,
-  LastInternalRelocation = 323,
+  LastInternalRelocation = 325,
 
-  /* 'QUALCOMM' vendor relocations: 192-195 are represented by 320-323 */
+  /* 'QUALCOMM' vendor relocations: 192-197 are represented by 320-325 */
   FirstQUALCOMMVendorRelocation = 320,
-  LastQUALCOMMVendorRelocation = 323,
+  LastQUALCOMMVendorRelocation = 325,
   QUALCOMMVendorRelocationOffset =
       FirstQUALCOMMVendorRelocation - FirstNonstandardRelocation,
 

lib/Target/RISCV/RISCVRelocator.cpp

@@ -213,6 +213,8 @@ RelocationDescMap RelocDescs = {
     INTERNAL_RELOC_DESC_ENTRY(R_RISCV_QC_E_BRANCH, applyJumpOrCall),
     INTERNAL_RELOC_DESC_ENTRY(R_RISCV_QC_E_32, applyAbs),
     INTERNAL_RELOC_DESC_ENTRY(R_RISCV_QC_E_CALL_PLT, applyJumpOrCall),
+    INTERNAL_RELOC_DESC_ENTRY(R_RISCV_QC_ACCESS_16, applyNone),
+    INTERNAL_RELOC_DESC_ENTRY(R_RISCV_QC_ACCESS_32, applyNone),
 };
 
 #undef INTERNAL_RELOC_DESC_ENTRY

test/RISCV/standalone/Relocs/R_RISCV_QC_ACCESS_16/Inputs/1.s

@@ -0,0 +1,39 @@
+
+  .text
+  .p2align 1
+
+  .option exact
+
+  .set test_zero, 0
+
+QUALCOMM:
+
+test_clw:
+  c.lw a0, 0(a2)
+  .reloc test_clw, R_RISCV_VENDOR, QUALCOMM
+  .reloc test_clw, R_RISCV_CUSTOM196, test_zero
+
+test_csw:
+  c.sw a0, 0(a2)
+  .reloc test_csw, R_RISCV_VENDOR, QUALCOMM
+  .reloc test_csw, R_RISCV_CUSTOM196, test_zero
+
+test_clbu:
+  c.lbu a0, 0(a2)
+  .reloc test_clbu, R_RISCV_VENDOR, QUALCOMM
+  .reloc test_clbu, R_RISCV_CUSTOM196, test_zero
+
+test_clh:
+  c.lh a0, 0(a2)
+  .reloc test_clh, R_RISCV_VENDOR, QUALCOMM
+  .reloc test_clh, R_RISCV_CUSTOM196, test_zero
+
+test_csb:
+  c.sb a0, 0(a2)
+  .reloc test_csb, R_RISCV_VENDOR, QUALCOMM
+  .reloc test_csb, R_RISCV_CUSTOM196, test_zero
+
+test_csh:
+  c.sh a0, 0(a2)
+  .reloc test_csh, R_RISCV_VENDOR, QUALCOMM
+  .reloc test_csh, R_RISCV_CUSTOM196, test_zero

test/RISCV/standalone/Relocs/R_RISCV_QC_ACCESS_16/R_RISCV_QC_ACCESS_16.test

@@ -0,0 +1,33 @@
+#---R_RISCV_QC_ACCESS_16.test------------------ Executable------------#
+#BEGIN_COMMENT
+#  Check that R_RISCV_QC_ACCESS_16 is correctly handled.
+#  It marks 16-bit compressed load and store instructions that are
+#  candidates for GP-relative linker relaxation from a QC_E_LI +
+#  compressed Load/Store sequence. Without relaxation, the instruction
+#  is left unchanged.
+#--------------------------------------------------------------------
+#END_COMMENT
+REQUIRES: riscv32
+#START_TEST
+RUN: %clang %clangopts -march=rv32ic_zcb -c %p/Inputs/1.s -o %t1.1.o
+RUN: %link %linkopts %t1.1.o -o %t1.out
+RUN: %objdump --no-print-imm-hex -M no-aliases -d %t1.out | %filecheck %s
+#END_TEST
+
+CHECK-LABEL: <test_clw>:
+CHECK: c.lw a0, 0(a2)
+
+CHECK-LABEL: <test_csw>:
+CHECK: c.sw a0, 0(a2)
+
+CHECK-LABEL: <test_clbu>:
+CHECK: c.lbu a0, 0(a2)
+
+CHECK-LABEL: <test_clh>:
+CHECK: c.lh a0, 0(a2)
+
+CHECK-LABEL: <test_csb>:
+CHECK: c.sb a0, 0(a2)
+
+CHECK-LABEL: <test_csh>:
+CHECK: c.sh a0, 0(a2)

test/RISCV/standalone/Relocs/R_RISCV_QC_ACCESS_32/Inputs/1.s

@@ -0,0 +1,49 @@
+
+  .text
+  .p2align 2
+
+  .option exact
+
+  .set test_zero, 0
+
+QUALCOMM:
+
+test_lb:
+  lb a0, 0(a1)
+  .reloc test_lb, R_RISCV_VENDOR, QUALCOMM
+  .reloc test_lb, R_RISCV_CUSTOM197, test_zero
+
+test_lbu:
+  lbu a0, 0(a1)
+  .reloc test_lbu, R_RISCV_VENDOR, QUALCOMM
+  .reloc test_lbu, R_RISCV_CUSTOM197, test_zero
+
+test_lh:
+  lh a0, 0(a1)
+  .reloc test_lh, R_RISCV_VENDOR, QUALCOMM
+  .reloc test_lh, R_RISCV_CUSTOM197, test_zero
+
+test_lhu:
+  lhu a0, 0(a1)
+  .reloc test_lhu, R_RISCV_VENDOR, QUALCOMM
+  .reloc test_lhu, R_RISCV_CUSTOM197, test_zero
+
+test_lw:
+  lw a0, 0(a1)
+  .reloc test_lw, R_RISCV_VENDOR, QUALCOMM
+  .reloc test_lw, R_RISCV_CUSTOM197, test_zero
+
+test_sb:
+  sb a0, 0(a1)
+  .reloc test_sb, R_RISCV_VENDOR, QUALCOMM
+  .reloc test_sb, R_RISCV_CUSTOM197, test_zero
+
+test_sh:
+  sh a0, 0(a1)
+  .reloc test_sh, R_RISCV_VENDOR, QUALCOMM
+  .reloc test_sh, R_RISCV_CUSTOM197, test_zero
+
+test_sw:
+  sw a0, 0(a1)
+  .reloc test_sw, R_RISCV_VENDOR, QUALCOMM
+  .reloc test_sw, R_RISCV_CUSTOM197, test_zero

test/RISCV/standalone/Relocs/R_RISCV_QC_ACCESS_32/R_RISCV_QC_ACCESS_32.test

@@ -0,0 +1,38 @@
+#---R_RISCV_QC_ACCESS_32.test------------------ Executable------------#
+#BEGIN_COMMENT
+#  Check that R_RISCV_QC_ACCESS_32 is correctly handled.
+#  It marks 32-bit load and store instructions that are candidates for
+#  GP-relative linker relaxation from a QC_E_LI + Load/Store sequence.
+#  Without relaxation, the instruction is left unchanged.
+#--------------------------------------------------------------------
+#END_COMMENT
+REQUIRES: riscv32
+#START_TEST
+RUN: %clang %clangopts -march=rv32i -c %p/Inputs/1.s -o %t1.1.o
+RUN: %link %linkopts %t1.1.o -o %t1.out
+RUN: %objdump --no-print-imm-hex -d %t1.out | %filecheck %s
+#END_TEST
+
+CHECK-LABEL: <test_lb>:
+CHECK: lb a0, 0(a1)
+
+CHECK-LABEL: <test_lbu>:
+CHECK: lbu a0, 0(a1)
+
+CHECK-LABEL: <test_lh>:
+CHECK: lh a0, 0(a1)
+
+CHECK-LABEL: <test_lhu>:
+CHECK: lhu a0, 0(a1)
+
+CHECK-LABEL: <test_lw>:
+CHECK: lw a0, 0(a1)
+
+CHECK-LABEL: <test_sb>:
+CHECK: sb a0, 0(a1)
+
+CHECK-LABEL: <test_sh>:
+CHECK: sh a0, 0(a1)
+
+CHECK-LABEL: <test_sw>:
+CHECK: sw a0, 0(a1)