[RISCV] Add support for R_RISCV_QC_ACCESS_16 and R_RISCV_QC_ACCESS_32#1139
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[RISCV] Add support for R_RISCV_QC_ACCESS_16 and R_RISCV_QC_ACCESS_32#1139lenary wants to merge 1 commit into
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These QUALCOMM vendor relocations mark 16-bit compressed and 32-bit load/store instructions as candidates for relaxation from a QC_E_LI + Load/Store sequence. This Change: - Extends the internal QUALCOMM relocation range to cover the new relocations - registers them with applyNone (marker semantics, no instruction changes), - and add tests covering loads, stores, and compressed instructions. Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com> Signed-off-by: Sam Elliott <aelliott@qti.qualcomm.com>
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These QUALCOMM vendor relocations mark 16-bit compressed and 32-bit load/store instructions as candidates for relaxation from a QC_E_LI + Load/Store sequence.
This Change:
This PR goes with llvm/llvm-project#188671 and quic/riscv-elf-psabi-quic-extensions#63 - the latter is necessary to understand how these relocations are intended to work.
This was written with the assistance of AI.