Add direct path from register to routing crossbar, bypassing FU#274
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tancheng merged 15 commits intotancheng:masterfrom Mar 15, 2026
Merged
Add direct path from register to routing crossbar, bypassing FU#274tancheng merged 15 commits intotancheng:masterfrom
tancheng merged 15 commits intotancheng:masterfrom
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guosran
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Jackcuii,
ShangkunLi,
n0thingNoob,
tancheng and
yyan7223
Use wider TileInType = mk_bits(clog2(num_tile_inports + num_fu_inports + 1)) to match the updated mk_ctrl routing_xbar_outport field width.
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tancheng
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Mar 13, 2026
- Renamed kAttrReadRegFrom to kAttrReadRegTowards in data_struct_attr.py - Changed field type from b1 to RegFromType (2-bit) in messages.py - Updated RegisterBankRTL.py to check read_reg_towards value: - 0: towards nothing (no read) - 1: towards FU (reg data consumed by operation) - 2: towards routing_xbar (reg data routed out to outport) - 3: towards both FU and routing_xbar - Updated RegisterClusterRTL.py to drive send_data_to_routing_crossbar.val based on read_reg_towards being 2 or 3 - Updated CtrlMemDynamicRTL.py field references - Updated all test files to use read_reg_towards with b2 type - Updated SV test files with new type names and field names This addresses the reviewer's request to reuse RegFromType for read_reg_towards to indicate whether FU expects inputs from inports or register.
tancheng
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Mar 13, 2026
…end_data_to_fu to send_data, simplify conditions
tancheng
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Mar 14, 2026
tancheng
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tancheng
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tancheng
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Description
This PR addresses issue #273 and coredac/neura#278. It introduces a direct pathway from the Register Cluster banks to the
routing_crossbar, allowingreg -> outportcommunication to bypass the FU.Summary of Changes
RegisterClusterRTL.py: Interfaced directsend_data_to_routing_crossbaroutputs.TileRTL.py&TileWithContextSwitchRTL.py: Connected the newly created register cluster outputs to the subsequent indices of the routing crossbar's input ports.messages.py: Expanded thetile_in_type_nbitsparameter to accommodate both the neighboring tile's input ports and the new register bank sources. Included this width parameter in the PyMTL cache name to ensure distinct control signal generation.Test Benches: Updated internal crossbar config sizes across multiple tests.