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Merged
tancheng merged 15 commits into from
Mar 15, 2026
Merged

Add direct path from register to routing crossbar, bypassing FU #274

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8f861cc
feat: add direct path from register to routing crossbar, bypassing FU
guosran Mar 13, 2026
d74442f
Merge branch 'master' into fix/reg-routing-bypass
guosran Mar 13, 2026
e242627
fix: update TileInType in test_readReg_routing_priority test
guosran Mar 13, 2026
8e4fe8a
Rename read_reg_from to read_reg_towards with 2-bit semantics
guosran Mar 13, 2026
7410573
Fix remaining b1 to b2 type conversions in read_reg_towards arrays
guosran Mar 13, 2026
8d227a7
refactor: move READ_TOWARDS_* constants to data_struct_attr, rename s…
guosran Mar 14, 2026
8a3c56e
Move READ_TOWARDS enums to common
guosran Mar 14, 2026
6fcc806
Updated TileRTL_test.py
guosran Mar 14, 2026
dec3a7f
Add tests
guosran Mar 14, 2026
40d7840
Edited tests for syntax updates
guosran Mar 14, 2026
887af9f
Corrected SV test files
guosran Mar 14, 2026
fbde2d5
Edited SV files and renamed constants
guosran Mar 14, 2026
4b66357
Disabled SV test
guosran Mar 15, 2026
e5d3155
Fix systolic SV tb: update packet hash and add explicit bit-widths to…
guosran Mar 15, 2026
da24f35
Re-enable SV tb CI step
guosran Mar 15, 2026
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24 changes: 12 additions & 12 deletions cgra/test/CgraRTL_fir_2x2_loop_counter_test.py
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Original file line number Diff line number Diff line change
Expand Up @@ -179,7 +179,7 @@ def line_trace(s):
num_cgras = num_cgra_columns * num_cgra_rows
num_ctrl_operations = 64
num_registers_per_reg_bank = 16
TileInType = mk_bits(clog2(num_tile_inports + 1))
TileInType = mk_bits(clog2(num_tile_inports + num_fu_inports + 1))
FuInType = mk_bits(clog2(num_fu_inports + 1))
FuOutType = mk_bits(clog2(num_fu_outports + 1))
addr_nbits = clog2(data_mem_size_global)
Expand Down Expand Up @@ -244,8 +244,8 @@ def line_trace(s):
write_reg_from_code = [b2(0) for _ in range(num_fu_inports)]
# 2 indicates the FU xbar port (instead of const queue or routing xbar port).
write_reg_from_code[0] = b2(2)
read_reg_from_code = [b1(0) for _ in range(num_fu_inports)]
read_reg_from_code[0] = b1(1)
read_reg_towards_code = [b2(0) for _ in range(num_fu_inports)]
read_reg_towards_code[0] = b2(1)
read_reg_idx_code = [RegIdxType(0) for _ in range(num_fu_inports)]

fu_in_code = [FuInType(x + 1) for x in range(num_fu_inports)]
Expand Down Expand Up @@ -442,7 +442,7 @@ def sim_fir_with_loop_counter(cmdline_opts, mem_access_is_combinational, has_ctr
TileInType(0), TileInType(0), TileInType(0), TileInType(0)],
[FuOutType(1), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0),
FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0)],
read_reg_from = [b1(1), b1(0), b1(0), b1(0)]))),
read_reg_towards = [b2(1), b2(0), b2(0), b2(0)]))),

# NAH.
IntraCgraPktType(0, 0,
Expand Down Expand Up @@ -496,7 +496,7 @@ def sim_fir_with_loop_counter(cmdline_opts, mem_access_is_combinational, has_ctr
TileInType(0), TileInType(0), TileInType(0), TileInType(0)],
[FuOutType(1), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0),
FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0)],
read_reg_from = [b1(1), b1(0), b1(0), b1(0)]))),
read_reg_towards = [b2(1), b2(0), b2(0), b2(0)]))),

# Launch the tile.
IntraCgraPktType(0, 1, payload = CgraPayloadType(CMD_LAUNCH))
Expand All @@ -522,7 +522,7 @@ def sim_fir_with_loop_counter(cmdline_opts, mem_access_is_combinational, has_ctr
TileInType(0), TileInType(PORT_EAST), TileInType(0), TileInType(0)],
[FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(1), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0),
FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0)],
read_reg_from = [b1(1), b1(0), b1(0), b1(0)]))),
read_reg_towards = [b2(1), b2(0), b2(0), b2(0)]))),
# ADD_CONST_LD.
IntraCgraPktType(0, 2,
payload = CgraPayloadType(CMD_CONFIG, ctrl_addr = 1,
Expand All @@ -542,7 +542,7 @@ def sim_fir_with_loop_counter(cmdline_opts, mem_access_is_combinational, has_ctr
TileInType(PORT_SOUTH), TileInType(0), TileInType(0), TileInType(0)],
[FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0),
FuOutType(1), FuOutType(0), FuOutType(0), FuOutType(0)],
read_reg_from = [b1(0), b1(1), b1(0), b1(0)],
read_reg_towards = [b2(0), b2(1), b2(0), b2(0)],
write_reg_from = [b2(2), b2(0), b2(0), b2(0)]))),

IntraCgraPktType(0, 2,
Expand Down Expand Up @@ -587,35 +587,35 @@ def sim_fir_with_loop_counter(cmdline_opts, mem_access_is_combinational, has_ctr
TileInType(0), TileInType(PORT_SOUTH), TileInType(0), TileInType(0)],
[FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0),
FuOutType(0), FuOutType(1), FuOutType(0), FuOutType(0)],
read_reg_from = [b1(1), b1(0), b1(0), b1(0)],
read_reg_towards = [b2(1), b2(0), b2(0), b2(0)],
write_reg_from = [b2(0), b2(2), b2(0), b2(0)]))),
# RET.
IntraCgraPktType(0, 3,
payload = CgraPayloadType(CMD_CONFIG, ctrl_addr = 1,
ctrl = CtrlType(OPT_RET,
# The first 2 indicates the first operand is from the second inport,
# which is actually from the second register cluster rather than the
# inport channel, indicated by the `read_reg_from_code`.
# inport channel, indicated by the `read_reg_towards_code`.
[FuInType(2), FuInType(0), FuInType(0), FuInType(0)],
[TileInType(0), TileInType(0), TileInType(0), TileInType(0), TileInType(0), TileInType(0), TileInType(0), TileInType(0),
TileInType(0), TileInType(0), TileInType(PORT_WEST), TileInType(0)],
[FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0),
FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0)],
read_reg_from = [b1(0), b1(1), b1(0), b1(0)],
read_reg_towards = [b2(0), b2(1), b2(0), b2(0)],
write_reg_from = [b2(0), b2(0), b2(1), b2(0)]))),
# PHI_CONST.
IntraCgraPktType(0, 3,
payload = CgraPayloadType(CMD_CONFIG, ctrl_addr = 2,
ctrl = CtrlType(OPT_PHI_CONST,
# The first 3 indicates the first operand is from the third inport,
# which is actually from the third register cluster rather than the
# inport channel, indicated by the `read_reg_from_code`.
# inport channel, indicated by the `read_reg_towards_code`.
[FuInType(3), FuInType(0), FuInType(0), FuInType(0)],
[TileInType(0), TileInType(0), TileInType(0), TileInType(0), TileInType(0), TileInType(0), TileInType(0), TileInType(0),
TileInType(0), TileInType(0), TileInType(0), TileInType(0)],
[FuOutType(0), FuOutType(0), FuOutType(1), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0),
FuOutType(1), FuOutType(0), FuOutType(0), FuOutType(0)],
read_reg_from = [b1(0), b1(0), b1(1), b1(0)],
read_reg_towards = [b2(0), b2(0), b2(1), b2(0)],
write_reg_from = [b2(2), b2(0), b2(0), b2(0)]))),

IntraCgraPktType(0, 3,
Expand Down
20 changes: 10 additions & 10 deletions cgra/test/CgraRTL_fir_2x2_test.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -182,7 +182,7 @@ def line_trace(s):
num_cgras = num_cgra_columns * num_cgra_rows
num_ctrl_operations = 64
num_registers_per_reg_bank = 16
TileInType = mk_bits(clog2(num_tile_inports + 1))
TileInType = mk_bits(clog2(num_tile_inports + num_fu_inports + 1))
FuInType = mk_bits(clog2(num_fu_inports + 1))
FuOutType = mk_bits(clog2(num_fu_outports + 1))
addr_nbits = clog2(data_mem_size_global)
Expand Down Expand Up @@ -247,8 +247,8 @@ def line_trace(s):
write_reg_from_code = [b2(0) for _ in range(num_fu_inports)]
# 2 indicates the FU xbar port (instead of const queue or routing xbar port).
write_reg_from_code[0] = b2(2)
read_reg_from_code = [b1(0) for _ in range(num_fu_inports)]
read_reg_from_code[0] = b1(1)
read_reg_towards_code = [b2(0) for _ in range(num_fu_inports)]
read_reg_towards_code[0] = b2(1)
read_reg_idx_code = [RegIdxType(0) for _ in range(num_fu_inports)]

fu_in_code = [FuInType(x + 1) for x in range(num_fu_inports)]
Expand Down Expand Up @@ -509,7 +509,7 @@ def sim_fir_return(cmdline_opts, mem_access_is_combinational, has_ctrl_ring):
FuOutType(0), FuOutType(1), FuOutType(0), FuOutType(0)],
# 2 indicates the FU xbar port (instead of const queue or routing xbar port).
write_reg_from = [b2(0), b2(2), b2(0), b2(0)],
read_reg_from = [b1(1), b1(0), b1(0), b1(0)]))),
read_reg_towards = [b2(1), b2(0), b2(0), b2(0)]))),

# ADD.
IntraCgraPktType(0, 1,
Expand All @@ -528,13 +528,13 @@ def sim_fir_return(cmdline_opts, mem_access_is_combinational, has_ctrl_ring):
ctrl = CtrlType(OPT_RET,
# The first 2 indicates the first operand is from the second inport,
# which is actually from the second register cluster rather than the
# inport channel, indicated by the `read_reg_from_code`.
# inport channel, indicated by the `read_reg_towards_code`.
[FuInType(2), FuInType(0), FuInType(0), FuInType(0)],
[TileInType(0), TileInType(0), TileInType(0), TileInType(0), TileInType(0), TileInType(0), TileInType(0), TileInType(0),
TileInType(0), TileInType(0), TileInType(0), TileInType(0)],
[FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0),
FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0)],
read_reg_from = [b1(0), b1(1), b1(0), b1(0)]))),
read_reg_towards = [b2(0), b2(1), b2(0), b2(0)]))),

IntraCgraPktType(0, 1,
payload = CgraPayloadType(CMD_CONFIG_PROLOGUE_FU, ctrl_addr = 0,
Expand Down Expand Up @@ -600,7 +600,7 @@ def sim_fir_return(cmdline_opts, mem_access_is_combinational, has_ctrl_ring):
TileInType(0), TileInType(PORT_SOUTH), TileInType(0), TileInType(0)],
[FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(1), FuOutType(0),
FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0)],
read_reg_from = [b1(1), b1(0), b1(0), b1(0)]))),
read_reg_towards = [b2(1), b2(0), b2(0), b2(0)]))),
# ADD_CONST_LD.
IntraCgraPktType(0, 2,
payload = CgraPayloadType(CMD_CONFIG, ctrl_addr = 1,
Expand Down Expand Up @@ -661,14 +661,14 @@ def sim_fir_return(cmdline_opts, mem_access_is_combinational, has_ctrl_ring):
ctrl = CtrlType(OPT_PHI_CONST,
# The first 2 indicates the first operand is from the second inport,
# which is actually from the second register cluster rather than the
# inport channel, indicated by the `read_reg_from_code`.
# inport channel, indicated by the `read_reg_towards_code`.
[FuInType(2), FuInType(0), FuInType(0), FuInType(0)],
[TileInType(0), TileInType(0), TileInType(0), TileInType(0), TileInType(0), TileInType(0), TileInType(0), TileInType(0),
TileInType(0), TileInType(0), TileInType(0), TileInType(0)],
[FuOutType(0), FuOutType(0), FuOutType(1), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(1),
FuOutType(1), FuOutType(0), FuOutType(0), FuOutType(0)],
write_reg_from = [b2(2), b2(0), b2(0), b2(0)],
read_reg_from = [b1(0), b1(1), b1(0), b1(0)]))),
read_reg_towards = [b2(0), b2(1), b2(0), b2(0)]))),

# INC_NE_CONST_NOT_GRT.
IntraCgraPktType(0, 3,
Expand All @@ -682,7 +682,7 @@ def sim_fir_return(cmdline_opts, mem_access_is_combinational, has_ctrl_ring):
FuOutType(0), FuOutType(2), FuOutType(0), FuOutType(0)],
# 2 indicates the FU xbar port (instead of const queue or routing xbar port).
write_reg_from = [b2(0), b2(2), b2(0), b2(0)],
read_reg_from = [b1(1), b1(0), b1(0), b1(0)]))),
read_reg_towards = [b2(1), b2(0), b2(0), b2(0)]))),
# NAH.
IntraCgraPktType(0, 3,
payload = CgraPayloadType(CMD_CONFIG, ctrl_addr = 2,
Expand Down
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