Add dot_row_reversed: the symmetric-table kernel (+ SMLALDX Q15 path)

[tap]

What

One new kernel in tap/dsp/fir_kernels.h:

dot_row_reversed(row, hist, taps)  →  Σₜ hist[t] · row[taps−1−t]

history walked forward, coefficient row read tap-reversed. This is the kernel a linear-phase polyphase table halved by symmetry needs: branch p of a symmetric prototype is branch L−1−p read in reverse, so the mirrored branches dot the stored row backward and the halving costs storage only. It lands here first per the substrate discipline — the consumer is RatioTap's M7 campaign, lever 3 (polyphase symmetry storage halving), and SampleRateTap can adopt the same structure later if it wants the bytes.

Bit-exactness contract

Pinned by the new typed parity test (ReversedMatchesMaterializedMirrorBitExact, float/Q15/Q31 × taps ∈ {44, 48, 33, 1, 2}): identical bits to dot_row against the materialized mirrored row — the t-th product and the ascending-t accumulation order are the same, float's fixed double accumulation included, single finalize.

On DSP-extension Arm cores (M33/M4/M7 class, same gate as dot_row's SMLALD path) the Q15 loop uses the swapped-lane dual MAC (SMLALDX): one 32-bit load per pair on each side — the row load at taps−2−t packs the two coefficients in cross order, and SMLALDX's lo×hi + hi×lo pairing is exactly the reversed walk. Each 16×16 product is exact in int32 and the int64 accumulation is associative, so pairing changes no output bit.

Verification

• 99/99 host tests (gcc Release; clang -Werror -Wconversion build also clean).
• Compile-smoked for cortex-m33 (-mcpu=cortex-m33, intrinsic path active) and cortex-m55 (MVE gate correctly disables the intrinsic).
• clang-tidy-18 clean.
• On-target bit-exactness of the SMLALDX pairing gets its end-to-end proof in RatioTap's M33 bare-metal suite when the consumer PR lands (the impulse-reproduces-table sweep runs through mirrored phases bit-exactly).

🤖 Generated with Claude Code

https://claude.ai/code/session_01Ldeq57sBySx2nFTQsGcQB6

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